About Piranha

Piranha · 2023-11-26

This is not a bug of the forum engine, but of the main ST web server! Let's open the following link:https://www.st.com/resource/en/application_note/an2606-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.pdfBy default on a Chromium/Bl...

Piranha · 2023-11-20

If one takes a link to a specific post, then the posts, which had been moved from other topics, show the title of their respective original topic.Original post (OK)Moved post (wrong title):Also, as I have reported previously, adding a "Re: " in front...

Piranha · 2023-11-09

Dragged a mouse accidentally over this post down there. Pressed at least one or both of the left/right mouse buttons at the same time. The screenshot has not been modified...The only interaction with the page, that still works:Scrolling. Also middle ...

Piranha · 2023-11-09

UM1974 Rev 10, Table 1. Ordering information:For the NUCLEO-F303ZE board the column "Differentiating features" lists an "Ethernet", which is false.Of course a deceptive photo and description just adds to the confusion...https://www.st.com/en/evaluati...

Piranha · 2023-11-05

Every day some alternatively gifted user creates a duplicate topics, people often comment on more than one of those and in the end the information is scattered in around and is a mess. For an example:https://community.st.com/t5/stm32-mcus-embedded-so...

Piranha · 2024-03-30

Are you capable of using Google?https://developer.arm.com/documentation/ddi0337/e/Instruction-Timing/Processor-instruction-timingshttps://developer.arm.com/documentation/ddi0337/h/programmers-model/instruction-set-summary/cortex-m3-instructions

Piranha · 2024-01-18

The FLASH I-cache on G4 is 1 KB, while the CPU I-cache on H5 is 8 KB and works also for SRAM and external memories. The FLASH prefetch is clearly explained in the RM0481 section 7.3.4. It's impact on performance is not so significant as from the I-ca...

Piranha · 2024-01-18

What I said was based on the observation how the old ST code with a broken ethernetif_input() function worked. The Rx packets were piling up in the DMA queue, because the code was not processing those. But it could also be anything from the million i...

Piranha · 2024-01-11

Your network input processing code assumes that one Rx interrupt means one Rx frame to process, but that is not true.And also read this:https://community.st.com/t5/stm32-mcus-embedded-software/how-to-make-ethernet-and-lwip-working-on-stm32/m-p/261456

Piranha · 2024-01-05

If a 10-20k pot is fine as a voltage divider, then obviously MCU output doesn't need additional buffering.

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ST web server bug for PDF files

Wrong topic title for moved posts

Modal fade of the page for no reason

Nucleo-144 documentation

Duplicate topics

Re: How many clock cycles does each assembly instruction require in STM32?

Re: STM32H562 FLASH Prefetch and ICACHE

Re: (Urgent)Inquiries about improving the response speed of device Ethernet communication

Re: (Urgent)Inquiries about improving the response speed of device Ethernet communication

Re: Controlling LCD Contrast and Backlight with microcontroller?