STM32 MCU datasheets: Expected preliminary updates

(Jul 2025)

Table 2. Device features and peripheral counts

Current:

Expected:

Jun 2026

STM32WL31xx

DS14836 Rev 1 (Feb 2025)

Figure 1. Block diagram

Expected:

Remove the SRAM1 from Block diagram figure

Jun 2026

STM32WL5MOC

DS14084 Rev 5

(Oct 2024)

Table 1. STM32WL5MOC features and peripheral counts

Current:

For ADC (number of channels, ext + int),

Expected:

For ADC (number of channels, ext + int), (of which two external channels cannot be used in STM32WL5MOCH6S)

Jun 2026

Current:

For GPIOs feature: 37 (35 on STM32WL5MOCH6S)

Expected:

For GPIOs feature: 37 (of which four GPIOs are used to control the STSAFE-A110 in STM32WL5MOCH6S)

Jun 2026

STM32F469xx

DS11189 Rev 8

(Nov 2023)

Table 2. STM32F469xx features and peripheral counts

Current:

Package for STM32F469Zx : LQPF

Expected:

Package for STM32F469Zx : "LQFP"

Jun 2025

Pinouts, pin description

and alternate functions

STM32H7B0xB

DS13196 Rev 7

(May 2022)

Table 14. Port G alternate functions

Current:

Alternate FMC Information is missing for PG15.

Expected:

Add FMC_SDNCAS alternate function for PG15.

Dec 2024

STM32H7B0xB

DS13196 Rev 7

(May 2022)

Table 7. STM32H7B0xB pin/ball definition

Current:

PG1 is FT_h2

Expected:

PG1 must be FT_ah2 due to OPAMP2_VINM analog additional function.

Dec 2024

STM32F373xx

D022691 Rev 7

(Jun 2016)

Table 12. Alternate functions for port PA.

Current:

Missing USB mapped on PA11-PA12 as AF14

Expected:

Add USB mapped on PA11-PA12 as AF14.

Apr
2024

STM32WBA6xxx

(Jul 2025)

Figure 14. UFBGA121_USB ballout

Figure 15. UFBGA121_SMPS_USB ballout

Current :

pin E1 named VEF+ in Figure 14. and Figure15 (page 76/77)

Expected:

Change VEF+ to VREF+

Sep 2025

STM32F722xx STM32F723xx

DS11853 Rev 9

(Jul 2022)

Figure 24. STM32F723xx UFBGA176 ballout

Current:

Figure name: STM32F723xx UFBGA176 ballout

Expected:

Figure name: STM32F722xx UFBGA176 ballout

Dec 2025

STM32F722xx STM32F723xx

DS11853 Rev 9

(Jul 2022)

Table 10. STM32F722xx and STM32F723xx pin and ball definition

Expected:

Add column for the VQFPN68 package

Dec 2025

STM32U375xx

(Feb 2026)

Table 20. Legend/abbreviations used in the pinout table

Expected:

For I/O structure, remove _t abbreviation line

Dec 2025

STM32WL5MOC

DS14084 Rev 5

(Oct 2024)

Table 4. STM32WL5MOC pin definition

Current:

For Pin number 1, the I/O structure is FT

Expected:

For Pin number 1, I/O structure is RST

Jun 2026

STM32H7S3x8 STM32H7S7x8 DS14359 Rev 7

(Jun 2026)

STM32H7R3x8 STM32H7R7x8 DS14360 Rev 6

(Jun 2026)

Table 21. STM32H7Sxx8 pin and ball descriptions

Current:

Note 4: XSPIM_P1 I/O and XSPIM_P2 I/O are supplied respectively by VDDXSPI1 and VDDXSPI2

Expected:

XSPIM_P1 I/O and XSPIM_P2 I/O are supplied respectively by VDDXSPI1 and VDDXSPI2. The EN_XSPIM1 and EN_XSPIM2 bits in PWR control register 2 (PWR_CSR2) must be set according to the selected XSPI interface.

Sep 2026

Electrical

Characteristics

STM32L552xx

DS12737 Rev 6

(Oct 2020)

Table 109. ADC characteristics

Current:

Missing VCMIN value.

Expected:

Add the VCMIN value

Dec 2025

STM32H725xE

STM32H725xG

DS13311 Rev 5

(Nov 2023)

Table 48. Flash memory programming

Current:

Sector (128 Kbytes) erase time for Program/erase parallelism X 64 is missing in Table 48. Flash memory programming

Expected:

Add a line with this information:

- Symbol : tERASE 128KB

- Parameter: Sector (128 Kbytes) erase time

- Conditions: Program/erase parallelism x 64

- Typ :1s

- Max: 2s

Sep 2025

STM32H523xx

DS14540 Rev 2

(Nov 2024)

STM32H533xx

DS14539 Rev 2

(Nov 2024)

Table . Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V

Current:

- The max value for Output valid time HS: 7/5

- Footnote (3). When using PB13 and PB14

Expected:

- For Output valid time HS, replace the max value '7/5' by 7/75'

- Replace the footnote (3): " When using PB13 & PB14" by "When using PB13"

Jun
2024

STM32U083xC

DS14463 Rev 2

(Mar 2024)

STM32U073x8

STM32U073xB

STM32U073xC

DS14548 Rev 2

(Mar 2024)

STM32U031x4

STM32U031x6/8

DS14581 Rev 2

(Mar 2024)

3.4.2 Embedded SRAM

Expected:

Delete the following sentence from SRAM description:

It is write-protected with a 1-Kbyte granularity.

Jun 2025

STM32H747xI/G

DS12930 Rev 3

(Jan 2026)

Table 53. DSI regulator characteristics

Current:

Parameter: Regulator output voltage on VDDDS

Expected:

Parameter: Regulator input voltage on VDDDS

Mar 2026

STM32H503xx

DS14053 Rev 4

(Oct 2024)

"12-bit ADC characteristics" section

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy"

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency" from the first paragraph in the "12-bit ADC characteristics" section.

Mar 2024

STM32H735xG

(Nov 2023)

"16-bit ADC characteristics" sub sections located in sections:

- Electrical characteristics (rev Y)

- Electrical characteristics (rev V) sections

Current:

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency "from the first paragraph.

Mar 2024

STM32H735xG

(Nov 2023)

Table 89. 12-bit ADC accuracy

Expected:

EG Typical = +/-2 LSBs

EG Max = +/-5 LSBs

May 2024

STM32F479xx

DS11118 Rev 8

(Nov 2023)

STM32F469xx

DS11189 Rev 8

(Nov 2023)

“ADC characteristics” table

Current:

Note 2 in the "ADC characteristics” table:

Based on test during characterization

Expected:

Update Note 2 to:

2. When VDDA and VREF+ are supplied by independent voltage sources, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V during the power-up phase.

Jun 2025

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx

(Feb 2026)

Figure xx. STM32U385xx power supply scheme (with SMPS)

Expected:

Remove the following sentence (page 94), in the note of Figure 25. STM32U385xx power supply scheme (with SMPS)

A 2.2 μH coil and a 2.2 μF capacitor on each VDD11 pin are then required.

Jun 2026

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx

DS14861 Rev3

(Feb 2026)

Table xx. Flash memory characteristics

Expected:

For tME, parameter: Mass erase time (two banks)

Typ: 11.9
Max: 13.2

Jun 2026

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx

(Feb 2026)

Table xx. 12-bit ADC characteristics

Expected:

The Max value for:

fADC, ADC clock frequency: 35

fs symbol:

For Resolution = 12 bits => Max: 2.5
For Resolution = 10 bits => Max: 2.92
For Resolution = 8 bits => Max: 3.5
For Resolution = 6 bits => Max: 4.375

Jun 2026

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx

(Feb 2026)

Table xx. Maximum RAIN for 12-bit ADC

Expected:

Remove the column “Sampling cycle at 55 MHz”

Jun 2026

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx

(Feb 2026)

Table 97. 12-bit ADC accuracy

Current:

Evaluated by characterization. Not tested in production.

Expected:

Evaluated by characterization on UFBGA package. Not tested in production.
Add the following note: “For more information on ADC accuracy, refer to the application note 'How to optimize the ADC accuracy in the STM32 MCUs' (AN2834).”

Jun 2026

STM32H757xI

DS12931 Rev 5

(Jan 2026)

STM32H742xI/G STM32H743xI/G

DS12110 Rev 11

(Jan 2026)

STM32H753xI

DS12117 Rev 10

(Jan 2026)

STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

DS12556 Rev 8

(Jan 2026)

STM32H755xI

DS12919 Rev 3

(Jan 2026)

STM32H745xI/G

DS12923 Rev 3

(Jan 2026)

STM32H747xI/G

DS12930 Rev 3

(Jan 2026)

STM32H757xI

DS12931 Rev 5

(Jan 2026)

PLL characteristics

Expected:

Replace VDDA by VDD in all “PLL characteristics” Tables.

Jun 2026

STM32N6x5xx STM32N6x7xx

DS14791 Rev 9

(Dec 2025)

Table 88. XSPI characteristics in DTR mode without DQS

Expected:

Add the following note in the tw(CS) row, for the value 3xt(CLK)

Note: XSPI_DCR1_CSHT[5:0] = 0x1

Jun 2026

STM32H7S3x8 STM32H7S7x8 DS14359 Rev 7

(Jun 2026)

STM32H7R3x8 STM32H7R7x8 DS14360 Rev 6

(Jun 2026)

Table x. General operating conditions

Expected:

Update the line relative to fcpu and delete note 9

Sep 2026

STM32H7S3x8 STM32H7S7x8 DS14359 Rev 7

(Jun 2026)

STM32H7R3x8 STM32H7R7x8 DS14360 Rev 6

(Jun 2026)

EXTI section

Expected:

Add the following section EXTI in section 6.3, after sub section “6.3.16 NRST pin characteristics”

Sep 2026

STM32C071x8

STM32C071xB

DS14693 Rev 2

(Apr 2025)

STM32C091xB

STM32C091xC

STM32C092xB

STM32C092xC

DS14720 Rev 3

(Mar 2026)

Table 28. Current consumption in Run mode from flash memory at different die temperatures

Expected:

IDD(Run) 32.768 kHz for Supply current in Run mode 25°C

Max = 0.120mA

Sep 2026

STM32N6x5xx STM32N6x7xx DS14791 Rev 10

(Aug 2026)

Table 120. Dynamic characteristics: Ethernet MAC signals for MDIO/SMA

Expected:

Add the following information:

Ethernet Primary interface GPIOs with advanced feature enabled configuration

ETH_RGMII_RXD[3:0], ETH_RGMII_TXD[3:0], ETH_RGMII_RX_CTL and ETH_RGMII_TX_CTL
GPIOx_ADVCFGRL_INVCLKx = 0x0
GPIOx_ADVCFGRL_DEx = 0x1
GPIOx_ADVCFGRL_RETx = 0x1
ETH_RGMII_RX_CLK and ETH_RGMII_TX_CLK
GPIOx_ADVCFGRL_INVCLKx = 0x0
GPIOx_ADVCFGRL_DEx = 0x0
GPIOx_ADVCFGRL_RETx = 0x0
GPIOx_ADVCFGRL->DLYPATHx = 0x1
With GPIOx_DELAYR[L|H]_DLY[3:0] = 0b0000 in RGMII mode
With GPIOx_DELAYR[L|H]_ DLY[3:0] = 0b1110 for RX_CLK, 0b1010 for TX_CLK in RGMII ID mode

Sep 2026

STM32N6x5xx STM32N6x7xx DS14791 Rev 10

(Aug 2026)

Features

Current:

In the section graphics (page 1)

• LCD-TFT controller up to XGA resolution

Expected:

• LCD-TFT controller up to 720p30, 24 bpp

Sep 2026

STM32F405xx STM32F407xx DS8626 Rev 12

(Mar 2026)

Table 67. ADC characteristics

Current:

Note 2: It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.

Expected:

2. When VDDA and VREF+ are supplied by independent voltage sources, during power-up phase, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V.

Sep 2026

STM32N6x5xx STM32N6x7xx DS14791 Rev 10

(Aug 2026)

Table 86. FMC SDRAM read timings

Expected:

Add the following information, above Table 86. FMC SDRAM read timings:

FMC primary interface GPIOs with timing retime feature enabled and peripheral configurations

SYSCFG_FMC_RETIMECR register (Tx, Rx paths and feedback clock)
SYSCFG_FMC_RETIMECR=0x02
(CFG_RETIME_RX=0, CFG_RETIME_TX=1, SDFBCLK_180=0)
FMC peripheral configuration in FMC_SDCR1 and FMC_SDCR2 register
Set RPIPE=1 and CAS[:10]=0x1

Sep 2026

STM32N6x5xx STM32N6x7xx DS14791 Rev 10

(Aug 2026)

108. DCMIPP characteristics

Add the following information, above Table 108. DCMIPP characteristics

DCMIPP Primary interface GPIOs with advanced feature enabled configuration

GPIOB:

GPIOB->ADVCFGRL=0xCC000000;

GPIOB->ADVCFGRH=0x0C0000CC;

GPIOD:

GPIOD->ADVCFGRL=0xC0CCC00C;

GPIOD->ADVCFGRH=0x00CCC00C;

GPIOE:

GPIOE->ADVCFGRL=0x0CC000CC;

GPIOE->ADVCFGRH=0x0000000C;

Sep 2026

STM32N6x5xx STM32N6x7xx DS14791 Rev 10

(Aug 2026)

Table 111. LCD-TFT characteristics:

Add the following information, above Table 111. LCD-TFT characteristics:

LTDC Primary interface GPIOs with advanced feature enabled and peripheral configurations

GPIO peripheral configuration:

LTDC_CLK (PA5) clock polarity retime configuration

GPIOA_ADVCFGRL_INVCLK5 = 0x1
GPIOA_ADVCFGRL_RET5 = 0x0
LTDC_[R|G|B]x, VSYNC,HSYNC,DE
GPIOx_ADVCFGRL_INVCLKx = 0x0
GPIOx_ADVCFGRL_RETx = 0x1
LTDC peripheral configuration :

LTDC_GCR->PCPOL=0x0

Sep 2026

Functional

overview

STM32WBA6xxx

(Jul 2025)

Figure 6. Clock tree

Expected:

Update UARTx to USARTx in Clock tree Figure

Sep 2025

STM32H747xI/G

DS12930 Rev 3

(Jan 2026)

3.5.1 Power supply scheme

Current:

- VDDDSI = 1.62 to 3.6 V: supply voltage for the DSI internal regulator

- VDD12DSI = 1.15 to 1.3 V: optional supply voltage for the DSI PHY (DSI regulator off)

- VCAPDSI: DSI regulator supply output

Expected:

- VDDDSI=1.62 to 3.6 V: supply voltage for the DSI internal regulator. If VDDDSI is not available, it is connected internally to VDD.

- VDD12DSI=1.15 to 1.3 V: DSI PHY supply input

- VCAPDSI: DSI regulator supply output. It must be connected to VDD12DSI if VDD12DSI pin is available; otherwise, it is connected internally to VCAPDSI.

Mar 2026

STM32H725xE/G

DS13311 Rev 5

(Nov 2023)

Table x. Timer feature comparison

Current:

The maximum timer clock is up to 550 MHz depending on the TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.

Expected:

The maximum timer clock is up to 275 MHz depending on the TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register.

Mar 2025

STM32H735xG

(Nov 2023)

STM32H733VG STM32H733ZG

DS13314 Rev 4

(Nov 2023)

STM32U083xC

DS14463 Rev 2

(Mar 2024)

STM32U073xx

DS14548 Rev 2

(Mar 2024)

Table 40. Current consumption in Stop 2 mode

Current:

For “LCD disabled” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “LCD disabled” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 41. Current consumption in Standby mode

Current:

For “No independent watchdog” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “No independent watchdog” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 42. Current consumption in Shutdown mode

Expected:

Remove in Conditions column: EN_ULP=0

Jun 2024

STM32H503xx

DS14053 Rev 4

(Oct 2024)

Table 33. Peripheral current consumption in Sleep mode

Current:

Table name: “Table 33. Peripheral current consumption in sleep mode”

Expected:

Change the name of the table to “Table 33. Peripheral current consumption”

Jun 2025

STM32H735xG

(Nov 2023)

Table 31. "Typical and maximum current consumption in Standby mode"

Current:

The max values are present for “RTC and LSE” ON

Expected:

The max values for “RTC and LSE” should be placed for “RTC and LSE” OFF

Aug 2024

STM32L4A6xG

DS11584 Rev 14

(Jul 2022)

Applicable for ALL STM32L4

3.29.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

Current:

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.

Expected:

TIM2 has a 32-bit auto-reload up/downcounter and 16-bit prescaler

Jun 2026

STM32H503xx

DS14053 Rev 4

(Oct 2024)

3.29 Controller area network (FDCAN)

Expected:

Add the following note at the end of the section:

Note: The WLCSP25 and UFQFPN32 devices do not support the HSE. When using FDCAN, the HSI can be used as the clock source via the PLL to drive the FDCAN. It is recommended to perform clock calibration to ensure the FDCAN clock source frequency remains within ±1.5%. For more details, please refer to AN6202, "How to Calibrate Internal RC Oscillators on STM32H5 MCUs.”

Jun 2026

STM32WBA5xxx

DS14127 Rev 10

(May 2026)

3.7 Boot modes

Current:

The bootloader is located in the system memory, programmed by ST during production. It is used to program the flash memory by using USART, I2C or SPI in device mode.

Expected:

Add text: "Availability of interfaces depend on package pinout and device supported peripherals."

Jun 2026

STM32WBA6xxx

(Jul 2025)

3.12.2 Power supply supervisor

In section “Standby mode”:

Current: The IWDG can remain active in Standby mode.

Expected: The IWDG, RTC, and TAMP can remain active in Standby mode.

Jun 2026

STM32WBA6xxx

(Jul 2025)

3.14.1 GPIO using PD6 and PD7

Expected:

Remove this section “3.14.1 GPIO using PD6 and PD7”

Jun 2026

STM32H5Exxx

DS14971 Rev 1

(Feb 2026)

3.42.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

Current:

Title: General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

Expected:

General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17)

Jun 2026

STM32U385xx

DS14830 Rev 3 (Feb 2026)

STM32U375xx