STM32 MCU datasheets: Expected preliminary updates

(Nov 2024)

Figure 1. STM32H5XXxx block diagram

Current:

Expected:

For USAR1, USART2, USART3, UART4, UART5, USART6 :

Update RTS by RTS_DE

Jun 2024

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

Table 2. STM32F446xC/E features and peripheral counts

Current:

Communication interfaces:

2 x SAI for STM32F446RE

Expected:

1 x SAI for STM32F446RE

Mar 2026

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

Figure 3. STM32F446xC/E block diagram

Expected:

Add note for SAI2:

* SAI2 is not available for LQFP64 package

Mar 2026

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

DS11532 Rev9

(Jul 2025)

Figure 1. Compatible board design for LQFP100 package

Current:

The following sentence under Figure 1:

The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are fully pin-to-pin compatible with STM32F4xx devices.

Expected:

Update the sentence as following:

The STM32F76x and STM32F4xx devices are indeed pin-to-pin compatible when not considering packages that include the DSI peripheral.

Mar 2026

STM32C5Axxx

(Feb 2026)

Description

Current:

The devices operate in the -40 to +105 °C (+140 °C junction) temperature ranges from a 2.7 to 3.6 V power supply.

Expected:

The devices operate in the -40 to +125 °C (+140 °C junction) temperature ranges from a 2.7 to 3.6 V power supply.

Mar 2026

Features and peripheral counts

STM32F469xx

DS11189 Rev8 (Nov 2023)

Table 2. STM32F469xx features and peripheral counts

Current:

Package for STM32F469Zx : LQPF

Expected:

Package for STM32F469Zx : "LQFP"

Jun 2025

Pinouts, pin description

and alternate functions

STM32H7B0xB

DS13196 Rev7

(May 2022)

Table 14. Port G alternate functions

Current:

Alternate FMC Information missing for PG15.

Expected:

Add FMC_SDNCAS alternate function for PG15.

Dec 2024

STM32H7B0xB

DS13196 Rev7

(May 2022)

Table 7. STM32H7B0xB pin/ball definition

Current:

PG1 is FT_h2

Expected :

PG1 must be FT_ah2 due to OPAMP2_VINM analog additional function.

Dec 2024

STM32H523xx

(Nov 2024)

Figure 11. UFBGA144 ballout

Expected:

Replace M12 by VSS

Jun 2024

STM32F373xx

D022691 Rev7

(Jun 2016)

Table 12. Alternate functions for port PA.

Current:

Missing USB mapped on PA11-PA12 as AF14

Expected:

Add USB mapped on PA11-PA12 as AF14.

Apr
2024

STM32WBA6xxx

DS14736 Rev3

(Jul 2025)

Figure 14. UFBGA121_USB ballout

Figure 15. UFBGA121_SMPS_USB ballout

Current :

pin E1 named VEF+ in Figure 14. and Figure15 (page 76/77)

Expected :

Change VEF+ to VREF+

Sep 2025

STM32F722xx STM32F723xx

(Jul 2022)

Figure 24. STM32F723xx UFBGA176 ballout

Current:

Figure 24. shows the ballout of the STM32F723xx UFBGA176 package

Expected:

Figure name: STM32F722xx UFBGA176 ballout

Dec 2025

STM32U375xx

DS14861 Rev3

(Feb 2026)

Table 20. Legend/abbreviations used in the pinout table

Expected:

For I/O structure, remove _t abbreviation line

Dec 2025

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

Table 11. Alternate function

Expected:

Remove this note in Table 11. Alternate function:

1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.*

Mar 2026

STM32F722xx STM32F723xx

(Jul 2022)

Table 10. STM32F722xx and STM32F723xx pin and ball definition

Expected:

Add column for the VQFPN68 package

Mar 2026

STM32F722xx STM32F723xx

(Jul 2022)

Figure 24. STM32F723xx UFBGA176 ballout

Current:

Figure name: STM32F723xx UFBGA176 ballout

Expected:

STM32F722xx UFBGA176 ballout

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 13. STM32C5A3xxx pin/ball definition

Expected:

Remove VFQFPN68 column

Mar 2026

Electrical

characteristics

STM32G491xC STM32G491xE

DS13122 Rev4

(Apr 2024)

5.2 Absolute maximum rating

Current:

The phrase "Exposure to maximum rating conditions for extended periods may affect device reliability" mentioned twice on the first lines of the Paragraph 5.2.

Expected:

Keep only one phrase.

Sep 2024

STM32L552xx DS12737 Rev6

(Oct 2020)

Table 109. ADC characteristics

Current:

Missing VCMIN value.

Expected:

Add the VCMIN value

Dec 2025

STM32WB55xx STM32WB35xx

DS11929 Rev17

(Oct 2024)

Table 28. RF receiver Bluetooth Low Energy characteristics (1 Mbps)

Current:

RSSI accuracy: Rssiaccu

Expected:

Add ±2 symbol for RSSI accuracy: ±2 dBm

Sep 2025

STM32H725xE/G

DS13311 Rev5

(Nov 2023)

Table 48. Flash memory programming

Current:

Sector (128 Kbytes) erase time for Program/erase parallelism X 64 is missing in Table 48. Flash memory programming

Expected:

Add a line with this information:

- Symbol : tERASE 128KB

- Parameter: Sector (128 Kbytes) erase time

- Conditions: Program/erase parallelism x 64

- Typ :1s

- Max: 2s

Sep 2025

STM32U385xx

DS14830 Rev2

(Feb 2025)

Table 86. I/O static characteristics

Current:

All I/Os except

FT_u, FT_d, FT_o,

FT_t,

TT_xx

Expected :

- Remove “FT_d” and change to:

All I/Os except

FT_u, FT_o,

FT_t,

TT_xx

Sep 2025

STM32U385xx

DS14830 Rev2

(Feb 2025)

Figure xx. I/O input characteristics (all I/Os except BOOT0)

Current:

Figure xx. I/O input characteristics (all I/Os except BOOT0)

Expected :

Change to :

Figure xx. I/O input characteristics

Sep 2025

STM32U385xx

DS14830 Rev2

(Feb 2025)

Table 98. Temperature sensor characteristics

Current:

Voltage at 30°C (±1 °C)

Expected :

Replace by:

Voltage at 30°C (±5 °C)

Sep 2025

STM32H757xI

DS12931 Rev4

(Apr 2025)

Table 99. ADC characteristics

Current:

Empty line in the page 185

Expected:

Remove empty line in the page 185

Dec 2025

STM32C011x4/x6

DS13866 Rev4

(Jan 2024)

Table 48. I/O current injection susceptibility

Current:

Note: 2. The injection current value is applicable when the switchable diode is activated, NA when not activated.

Expected:

Remove the Note 2 under Table 48

Dec 2025

STM32U385xx

DS14830 Rev2 (Feb 2025)

Table 24. Voltage characteristics

Current:

- For VIN

Ratings: Input voltage on FT_t and FT_o pins in VBAT mode
Max: Min (min (VBAT, VDDA, VDDUSB, VDDIO2) + 4.0, 6.0)

Expected:

- For VIN, replace by

Ratings: Input voltage on PC13 and FT_o pins in VBAT mode
Max: 4.0

- Remove PC13 line

Dec 2025

STM32U385xx

DS14830 Rev2 (Feb 2025)

5.3.8 External clock timing characteristics

Current:

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator.

Expected:

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic resonator oscillator.

Dec 2025

STM32U385xx

DS14830 Rev2 (Feb 2025)

Table 60. Current consumption during wake-up from Stop 3 mode on SMPS

Current:

Unit: µA

Expected:

Unit: nAs

Dec 2025

STM32F405xx, STM32F407xx

DS8626 Rev10

Table 45. ESD absolute maximum ratings

Current:

VESD(CDM)

Conditions: TA = +25 °C conforming to ANSI/ESD STM5.3.1
Maximum value : 500

Expected:

VESD(CDM)

Conditions : ANSI/ESDA/JEDEC JS-002
Maximum value : 250

Dec 2025

STM32H523xx

(Nov 2024)

STM32H533xx

DS14539 Rev2

(Nov 2024)

Table . Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V

Current:

- The max value for Output valid time HS: 7/5

- Footnote (3). When using PB13 and PB14

Expected:

- For Output valid time HS, replace the max value '7/5' by 7/75'

- Replace the footnote (3): " When using PB13 & PB14" by "When using PB13"

Jun
2024

STM32U083xC

DS14463 Rev2

(Mar 2024)

STM32U073x8/B/C

DS14548 Rev2

(Mar 2024)

STM32U031x4/6/8

DS14581 Rev2

(Mar 2024)

3.4.2 Embedded SRAM

Expected:

Delete the following sentence from SRAM description:

It is write-protected with a 1-Kbyte granularity.

Jun 2025

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

Figure 27. LACCHSI versus temperature

Current:

Figure name: "LACCHSI versus temperature”

Expected:

Figure name: "ACCHSI versus temperature”

Mar 2026

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

Figure 27. LACCHSI versus temperature

Current:

The values of the x-axis label are -40,0,25,5,8,105,125.

Expected:

The values of the x-axis are -40,0,25,55,85,105,125.

Mar 2026

STM32H747xI/G

DS12930 Rev3

(Jan 2026)

Table 53. DSI regulator characteristics

Current:

Parameter: Regulator output voltage on VDDDS

Expected:

Parameter: Regulator input voltage on VDDDS

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 60. Temperature sensor characteristics

Expected:

Remove the lines containing ADC counter:

- VSENSE linearity with temperature (from ADC counter)

- Average slope (from ADC counter)

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 47. I/O current injection susceptibility

Current:

Injected current on PA4 pins

Expected:

Update the line to add the pins :

Injected current on PA4, PB15, PD8, PD9 and PD13 pins

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 49. Output voltage characteristics (all I/Os except PC14 and PC15)

Expected:

In “Max” column: remove VDD from 0.4VDD

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 50. Output voltage characteristics for PC14 and PC15

Expected:

In “Max” column: replace “0” by 0.4

In “Min” column replace “2” by “2.4”

Mar 2026

Functional overview

STM32WBA6xxx

DS14736 Rev3

(Jul 2025)

Figure 6. Clock tree

Update UARTx to USARTx in Clock tree Figure

Sep 2025

STM32H747xI/G

DS12930 Rev3

(Jan 2026)

3.5.1 Power supply scheme

Current:

- VDDDSI = 1.62 to 3.6 V: supply voltage for the DSI internal regulator

- VDD12DSI = 1.15 to 1.3 V: optional supply voltage for the DSI PHY (DSI regulator off)

- VCAPDSI: DSI regulator supply output

Expected:

- V_DDDSI=1.62 to 3.6 V: supply voltage for the DSI internal regulator. If V_DDDSI is not available, it is connected internally to VDD.

- V_DD12DSI=1.15 to 1.3 V: DSI PHY supply input

- V_CAPDSI: DSI regulator supply output. It must be connected to V_DD12DSIif VDD12DSI pin is available; otherwise, it is connected internally to V_CAPDSI.

Mar 2026

STM32C5Axxx

(Feb 2026)

Table 7. Timer feature comparison

Expected:

Add TIM3 and TIM4 with TIM2 and TIM5 as 32-bit timers.

Mar 2026

STM32C5Axxx

(Feb 2026)

3.34 Ethernet (ETH): media access control (MAC) with DMA controller

Current:

• OPEN Alliance 10BASE-T1S PMD Transceiver Interface version 1.5

Expected:

Remove this line

Mar 2026

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

3.23 Universal synchronous/asynchronous receiver transmitters (USART)

Current:

The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, and UART5).

Expected:

The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4, and UART5).

Mar 2026

STM32F446xC/E

DS10693 Rev10 (Jan 2021)

3.23 Universal synchronous/asynchronous receiver transmitters (USART)

Current:

The USART1 and USART6 interfaces are able to communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s.

Expected:

The USART1 and USART6 interfaces are able to communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 Mbit/s.

Mar 2026

STM32H725xE/G

DS13311 Rev5

(Nov 2023)

Table 5. Timer feature comparison

Current:

1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.

Expected:

The maximum timer clock is up to 275 MHz depending on the TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register.

Mar 2025

STM32H735xG

(Nov 2023)

STM32H733VG STM32H733ZG

DS13314 Rev4

(Nov 2023)

Table 4. Timer feature comparison

Operating conditions

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

DS12110Rev10

(Mar 2023)

Table "General operating conditions" located in sections:

- Electrical characteristics (rev Y)

- Electrical characteristics (rev V) sections

Expected:

Remove "Ambient temperature for the suffix 3 version" line.

Apr 2024

STM32U083xC

DS14463 Rev2

(Mar 2024)

STM32U073xx

DS14548 Rev2

(Mar 2024)

Table 40. Current consumption in Stop 2 mode

Current:

For “LCD disabled” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “LCD disabled” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 41. Current consumption in Standby mode

Current:

For “No independent watchdog” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “No independent watchdog” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 42. Current consumption in Shutdown mode

Expected:

Remove in Conditions column: EN_ULP=0

Jun 2024

STM32F479xx

DS11118 Rev8

(Nov 2023)

STM32F469xx

DS11189 Rev8 (Nov 2023)

Table 45. MIPI D-PHY characteristics

Current:

Expected:

Jun 2025

STM32H503xx

DS14053 Rev4

(Oct 2024)

Table 33. Peripheral current consumption in Sleep mode

Current:

Table name: “Table 33. Peripheral current consumption in sleep mode”

Expected:

Change the name of the table to “Table 33. Peripheral current consumption”

Jun 2025

STM32H755xI

DS12919 Rev2

(Feb 2023)

Figure 16. External components for SMPS step-down converter

Expected:

Add this note to the title “Direct SMPS supply”:

Note : VOS0 can't be selected in Direct SMPS supply mode

Jun 2025

STM32H503xx

DS14053 Rev4

(Oct 2024)

Table 31

. Typical and maximum current consumption in Standby mode

Table 32. Typical and maximum current consumption in VBAT mode

Expected:

Jun 2025

STM32H735xG

(Nov 2023)

Table 31. "Typical and maximum current consumption in Standby mode"

Current:

The max values are present for “RTC and LSE” ON

Expected:

The max values for “RTC and LSE” should be placed for “RTC and LSE” OFF

Aug 2024

FMC

STM32H523xx

(Apr 2024)

FMC characteristics section

Current:

Missing Figure “Asynchronous multiplexed PSRAM/NOR write waveforms”

Expected:

Add this figure.

Jun

2024

STM32H7S3x8 STM32H7S7x8

DS14359 Rev4

(Nov 2024)

SDRAM waveforms and timings

Expected:

In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values:

For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 125 MHz at 20 pF
For 1.71 V<VDD<1.9 V: maximum FMC_CLK = 95 MHz at 20 pF
For 1.71 V<DD<1.9 V: maximum FMC_CLK = 100 MHz at 15 pF

Aug 2024

STM32H7R3x8 STM32H7R7x8

DS14360 Rev3

(Mar 2024)

Aug 2024

ADC

STM32H503xx

DS14053 Rev4

(Oct 2024)

"12-bit ADC characteristics" section

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy"

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency" from the first paragraph in the "12-bit ADC characteristics" section.

Mar 2024

STM32H735xG

(Nov 2023)

"16-bit ADC characteristics" sub sections located in sections:

- Electrical characteristics (rev Y)

- Electrical characteristics (rev V) sections

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy: General operating conditions".

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency"from the first paragraph.

Mar 2024

STM32H735xG

(Nov 2023)

Table 89. 12-bit ADC accuracy

Current:

Expected:

EG Typical = +/-2 LSBs

EG Max = +/-5 LSBs

May 2024

STM32F479xx

DS11118 Rev8

(Nov 2023)

STM32F469xx

DS11189 Rev8 (Nov 2023)

“ADC characteristics” table

Current:

Note 2 in the "ADC characteristics” table

Based on test during characterization

Expected:

Update Note 2 to:

2. When VDDA and VREF+ are supplied by independent voltage sources, it is recommended to maintain the difference between VDDA and VREF+ below 1.8V during the power-up phase.

Jun 2025

Package information

STM32F722xx STM32F723xx

(Jul 2022)

Table 125. Package thermal characteristics

Expected:

Add this parameter:

Thermal resistance junction-ambient

VFQFPN68 – 8 x 8 mm / 0.5 mm pitch

Value: 24.6

Mar 2026

STM32C5Axxx