STM32 MCU datasheets: Expected preliminary updates

(Apr 2024)

STM32H523xx

(Apr 2024)

Table xx. STM32H5XXxx pin/ball definition

Table xx. Alternate function AF0 to AF7

Table xx. Alternate function AF8 to AF15

Current:

The following name to update:

- LPUART1_RTS

- USART1_RTS

- USART2_RTS

- USART3_RTS

- UART4_RTS

- UART5_RTS

- USART6_RTS

Expected:

The correct name should be:

- LPUART1_RTS/LPUART1_DE

- USART1_RTS/USART1_DE

- USART2_RTS/USART2_DE

- USART3_RTS/USART3_DE

- UART4_RTS/UART4_DE

- UART5_RTS/UART5_DE

- USART6_RTS/USART6_DE

Jun
2024

STM32H523xx

(Apr 2024)

Figure 11. UFBGA144 ballout

Expected:

Replace M12 by VSS in figure 11

Jun 2024

STM32H7S3x8 STM32H7S7x8

DS14359 Rev2

(Mar 2024)

Table 22. STM32H7Sxx8 pin alternate functions

Current:

Missing Port (PG12 to PG15)

Expected:

Add the missing Port (PG12 to

PG15) to be integrated in Port G.

Aug 2024

STM32H7R3x8 STM32H7R7x8

DS14360 Rev2

(Mar 2024)

Table 20. STM32H7Rxx8 pin alternate functions

Current:

Missing Port (PG12 to PG15)

Expected:

Add the missing Port (PG12 to

PG15) to be integrated in Port G.

Aug 2024

STM32U5Gxxx

DS14102 Rev1

(Aug 2023)

STM32U5Fxxx

DS14395 Rev1

(Aug 2023)

Table 27. STM32U5Gxxx pin/ball definitions

Table 26. STM32U5Fxxx pin/ball definitions

Expected:

Add the following notes for pins names: PC13, PC14-
OSC32_IN (PC14) and PC15-
OSC32_OUT (PC15):

2. PC13, PC14, and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs in output mode is limited:
- The speed must not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).

3. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.

For PB15 and PA15 (JTDI) pins, add this note:

4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15 (UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.

Add this note for pins names: PA11 and PA12 :

5. GPIO is 5V-tolerant when the USB PHY is powered on.

Add the following note for pins names: PA13 (JTMS/SWDIO), PA14 (JTCK/SWCLK), PA15 (JTDI) and PB4 (NJTRST) :

6. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Sep 2024

STM32H523xx

(April 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Figure x. LQFP64 pinout

Current :

- VSSA

- VDDA

Expected:

Update VSSA by: VSSA/VREF-

Update VDDA by: VDDA/VREF+

Oct 2024

I/O port characteristics

STM32H533xx

(Apr 2024)

STM32H523xx

(Apr 2024)

Figure 20. VIL/VIH for all I/Os except BOOT0

Current:

Expected:

Jun 2024

Electrical

characteristics

STM32G491xC STM32G491xE

DS13122 Rev4

(Apr 2024)

5.2 Absolute maximum rating

Current:

The phrase "Exposure to maximum rating conditions for extended periods may affect device reliability" mentioned twice on the first lines of the Paragraph 5.2.

Expected:

Keep only one phrase.

Sep 2024

STM32G0C1xC

/xE

DS13564 Rev4

(Dec 2022)

Table 21. Voltage characteristics

Current:

Expected:

Add this line

Symbol	Ratings	Min	Max	Unit
VIN⁽¹⁾	FT_s	-0.3	VDDIO2+4.0 ⁽²⁾	V

Sep 2024

STM32WL5MOC

DS14084 Rev4 (February 2024)

5.2 Power consumption

Expected:

Add these tables where are listed the RF output power and the sensitivity for Sigfox modulation:

Table 1 Sigfox RF output power (T = 25 °C, VDD = 3.3 V)

Parameter	Condition	Min	Typ	Max	Unit
Frequency range		863		928	MHz
RF output power	RC1	12	12.3	-	dBm
	RC2	18	18.2	-
	RC3	11.7	11.9	-
	RC4	18.3	18.4	-
	RC5	11.1	11.2	-
	RC6	12.3	12.4	-
	RC7	12.3	12.5	-
Modulation techniques	Sigfox

Table 2 Sigfox receiver sensitivity (T = 25 °C, VDD = 3.3 V)

Zone	Frequency	Sensitivity (0.6 kbps)	Unit
RC1	869.525	-124.3	dBm
RC2	905.2	-122.2	dBm
RC3	922.2	-123.9	dBm
RC4	922.3	-122.4	dBm
RC5	922.3	-125.2	dBm
RC6	866.3	-124.4	dBm
RC7	869.1	-124.5	dBm

Oct 2024

RTC

STM32F405xx STM32F407xx

DS8626 Rev9

(Aug 2020)

2.2.18 Real-time clock (RTC), backup SRAM and backup registers

Current:

RTC can be clocked by HSE/128:

“It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128.”

Expected:

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 2 to 31.

Apr 2024

STM32F405xx STM32F407xx

DS8626 Rev9

(Aug 2020)

Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz)

Current:

The unit of fosc_IN is Mhz.

Expected:

The unit of fosc_IN should be Khz.

Apr 2024

STM32H735xG

DS13312 Rev4

(Nov 2023)

Table 31. "Typical and maximum current consumption in Standby mode"

Current:

The max values are present for “RTC and LSE” ON

Expected:

The max values for “RTC and LSE” should be placed for “RTC and LSE” OFF

Aug 2024

RCC

STM32WL33xx

(June 2024)

Figure 8. Fast clock tree generation

Current:

Expected:

- Replace CK_MR_SUBGHzWKUP by CLK_MR_SUBGHz_WKUP

- Replace CK_BUBBLE_WKUP by CLK_LPAWUR_WKUP

Sep 2024

USART

/

UART

STM32H533xx

(Apr 2024)

STM32H523xx

(Apr 2024)

Figure 1. STM32H5XXxx block diagram

Current:

Expected:

For USAR1, USART2, USART3, UART4, UART5, USART6 :

Update RTS by RTS_DE

Jun 2024

TIM

STM32H757xI

DS12931 Rev3

(Mar 2024)

Tables "Port B alternate functions" and "Port H alternate functions”

Current:

TIM12 AFs are missing in the tables "Port B alternate functions" and "Port H alternate functions" and should be mapped in the AF2

Expected:

Add TIM12 AFs in the tables "Port B alternate functions" and "Port H alternate functions" and should be mapped in the AF2.

Aug 2024

STM32H523xx

(April 2024)

STM32H533xx

(Apr 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Table xxx. LPTIMx characteristics

Expected:

to replace:

tTIMxCLK by t_{lptim_ker_ck}

fLPTIMxCLK by f_{lptim_ker_ck}

Oct 2024

TAMPER

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

(Mar 2023)

Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts

Current:

The wakeup pins and tamp pins of STM32H743AI are inverted.

Tamper pins : 5
Wakeup pins : 2

Expected :

Replace by :

Tamper pins : 2
Wakeup pins : 5

Apr 2024

Operating conditions

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

(Mar 2023)

Table "General operating conditions" located in sections:

- Electrical characteristics (rev Y)

- Electrical characteristics (rev V) sections

Current:

Expected:

Remove "Ambient temperature for the suffix 3 version" line.

Apr 2024

STM32G031x4

/x6/x8

DS12992 Rev3

(Oct 2021)

Table. Current consumption in Standby mode

Current:

ULPEN = 0

Expected:

Replace the ULPEN = 0 by ENB_ULP=0.

May 2024

STM32G0C1xC

/xE

DS13564 Rev4

(Dec 2022)

STM32G041x6

/x8

DS12993 Rev3

(Oct 2021)

STM32G071x8

/xB

DS12232 Rev4

(Sep 2021)

STM32G051x6

/x8

DS13303 Rev3

(Nov 2021)

STM32G061x6

/x8

DS13513 Rev3

(Nov 2021)

STM32G081xB

DS12231 Rev4

(Sep 2021)

STM32U083xC

DS14463 Rev2

(Mar 2024)

STM32U073xx

DS14548 Rev2

(Mar 2024)

Table 40. Current consumption in Stop 2 mode

Current:

For “LCD disabled” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “LCD disabled” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 41. Current consumption in Standby mode

Current:

For “No independent watchdog” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “No independent watchdog” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 42. Current consumption in Shutdown mode

Expected:

Remove in Conditions column: EN_ULP = 0

Jun 2024

STM32H533xx

(Apr 2024)

STM32H523xx

(Apr 2024)

Table xx. Maximum allowed clock frequencies

Current:

Symbol: "fadc_ker_ck "
Expected:

Replace by "fadc_ker_ck_input"

Jun 2024

STM32H523xx

(April 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Table xx. 12-bit ADC characteristics

Expected:

- Replace all f_ADC occurrences by "fadc_ker_ck"

- Add note (6) for fadc_ker_ck:

6- This clock frequency is only the analog ADC specification; it also needs to respect the Table xx Maximum allowed clock frequencies.

Oct 2024

STM32H503xx

DS14053 Rev4

(October 2024)

STM32H523xx

(April 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Table xx. Maximum allowed clock frequencies

Current :

- fdac_pclk

- fusb_ker_ck

Expected :

To replace by:

- fdac_ker_ck

- fucpd_ker_ck

Add note (3) for fadc_ker_ck⁽³⁾:

3. This maximum kernel clock frequency does not consider the maximum ADC clock frequency (refer to table xx. 12-bit ADC characteristics)

Oct 2024

STM32H533xx

(Apr 2024)

Table 20. General operating conditions

Current:

See Table 137 for appropriate thermal resistance and package.

Expected:

See Table 130 for appropriate thermal resistance and package.

Jun 2024

STM32H523xx

(Apr 2024)

Table 19. General operating conditions

Current:

See Table 137 for appropriate thermal resistance and package.

Expected:

See Table 129 for appropriate thermal resistance and package.

Jun 2024

STM32WL33xx

DS14264 Rev4

(Jun 2024)

Table 26. RF receiver characteristics

Current:

Expected:

Remove the TBD from table 26 and replace it with 176-j265.

Aug 2024

STM32H7S3x8 STM32H7S7x8

DS14359 Rev2

(Mar 2024)

Table xx. General operating conditions

Current:

Expected:

On the line 600 MHz add a note: ECC should be disabled.

Aug 2024

STM32H7R3x8 STM32H7R7x8

DS14360 Rev2

(Mar 2024)

Aug 2024

STM32WL33xx

(Jun 2024)

Table 26. RF receiver characteristics

Current :

Typical value for Input impedance at LNA : TBD

Expected :

Replace TBD by: 176 - j265

Sep 2024

STM32WL33xx

(Jun 2024)

Table 41. Current consumption in transmission mode, fc = 169 MHz

Current:

Expected:

Parameter	Symbol	Test condition	Unit
Supply current	Measurements TX @ CW 10 dBm TX pin connected, TX Mode	11	mA
Supply current	Measurements TX @ CW 16 dBm TXHP pin connected, TXHP mode	28	mA

Sep 2024

STM32H573xx

(May 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Table xx. Typical and maximum current consumption in VBAT mode

Current:

Expected:

Oct 2024

FMC

STM32H533xx

(Apr 2024)

STM32H523xx

(Apr 2024)

FMC characteristics section

Current:

Missing Figure “Asynchronous multiplexed PSRAM/NOR write waveforms”

Expected:

Add this figure.

Jun
2024

STM32H7S3x8 STM32H7S7x8

DS14359 Rev2

(Mar 2024)

SDRAM waveforms and timings

Current:

Expected:

In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values:

For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 125 MHz at 20 pF
For 1.71 V<VDD<1.9 V: maximum FMC_CLK = 95 MHz at 20 pF
For 1.71 V<DD<1.9 V: maximum FMC_CLK = 100 MHz at 15 pF

Aug 2024

STM32H7R3x8 STM32H7R7x8

DS14360 Rev2

(Mar 2024)

Aug 2024

ADC

STM32H503xx

DS14053 Rev4

(October 2024)

"12-bit ADC characteristics" section

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy"

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency" from the first paragraph in the "12-bit ADC characteristics" section.

Mar 2024

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

(Mar 2023)

"16-bit ADC characteristics" sub sections located in sections:

- Electrical characteristics (rev Y)

- Electrical characteristics (rev V) sections

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy: General operating conditions".

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency"from the first paragraph.

Mar 2024

STM32H753xI

DS12117 Rev9

(Mar 2023)

Mar 2024

STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

DS12556 Rev7

(Mar 2023)

Mar 2024

STM32H735xG

DS13312 Rev4

(Nov 2023)

Mar 2024

STM32H735xG

DS13312 Rev4

(Nov 2023)

Table 89. 12-bit ADC accuracy

Current:

Expected:

EG Typical = +/-2 LSBs

EG Max = +/-5 LSBs

May 2024

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

(Mar 2023)

Figure 1. STM32H742xI/G block diagram

Figure 2. STM32H743xI/G block diagram

Current:

In Figure 1. STM32H742xI/G block diagram:

1- Up to 20 analog inputs common to ADC1 & 2.

2- Up to 17 analog inputs common to ADC1 and 2

Expected:

To replace by:

1- Up to 20 analog inputs

Most are common to ADC1 & 2

2- Up to 17 analog inputs

Some common to ADC1 and 2

Apr
2024

STM32H747xI
STM32H747xG

DS12930 Rev2

(Mar 2023)

Figure 1. STM32H747xI/G block diagram

Apr
2024

STM32WL33xx

(Jun 2024)

3.24 Analog digital converter (ADC)

Current :

Battery level conversion up to 3.7 V

Expected:

Battery level conversion up to 3.6 V

Sep 2024

Memory

STM32H573xx

(May 2024)

Table 52. "Flash memory programming"

Current:

Expected:

Mar 2024

STM32H562xx

and

STM32H563xx

(May 2024)

Table 51. Flash memory programming

Current:

Expected:

Mar 2024

STM32H523xx

(Apr 2024)

STM32H533xx

(Apr 2024)

Table 49. Flash memory programming

Current:

Expected:

Jun
2024

STM32H523xx

(Apr 2024)

STM32H533xx

(Apr 2024)

Table . Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V

Current:

- The max value for Output valid time HS: 7/5

- Footnote (3). When using PB13 and PB14

Expected:

- For Output valid time HS, replace the max value '7/5' by 7/75'

- Replace the footnote (3): " When using PB13 & PB14" by "When using PB13"

Jun
2024

DCMI

STM32U5Axxx

DS13543 Rev2

(July 2023)

Digital camera interface (DCMI)

Current:

The DCMI is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).

Expected:

The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).

Oct 2024

STM32U5Fxxx

DS14395 Rev1

(August 2023)

STM32U5Gxxx

DS14102 Rev1

(August 2023)

STM32H562xx and STM32H563xx

(May 2024)

Current:

DCMI is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module, supporting YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG) formats.

Expected:

The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).

Oct 2024

STM32H573xx

(May 2024)

STM32H523xx

(April 2024)

STM32H533xx

(April 2024)

SDMMC

STM32H523xx

(Apr 2024)

STM32H533xx

(Apr 2024)

Table . SDMMC features

Current:

Expected:

Remove the SDMMC2 column, since the SDMMC2 is not available on STM32H523/533 devices

Jun
2024

STM32H523xx

(Apr 2024)

STM32H533xx

(Apr 2024)

Table . Dynamic characteristics: SD/MMC characteristics, VDD = 2.7 to 3.6 V

Current:

Footnote: 3. When using PB13 & PB14

Expected:

Replace the footnote 3 " When using PB13 & PB14" by "When using PB13"

Jun
2024

SPI

STM32H523xx

(April 2024)

Table 10. SPI features

Current:

Expected:

SPI feature	SPI1, SPI2, SPI3 (full feature set instances)	SPI4 (full feature set instances)
Data size	Configurable from 4 to 32-bit	Configurable from 4 to 16 bits
CRC computation	CRC polynomial length configurable from 5 to 33-bit	CRC polynomial length configurable from 5 to 17 bits
Size of FIFOs	16x 8-bit	8x8 bits
Number of transferred data	Up to 65536	Up to 65536
I2S feature	Yes	No

Oct 2024

STM32H573xx

(May 2024)

STM32H562xx

and

STM32H563xx

(May 2024)

Table xx. SPI features

Current:

Expected:

SPI feature	SPI1, SPI2, SPI3 (full feature set instances)	SPI4, SPI5, SPI6 (full feature set instances)
Data size	Configurable from 4 to 32-bit	Configurable from 4 to 16 bits
CRC computation	CRC polynomial length configurable from 5 to 33-bit	CRC polynomial length configurable from 5 to 17 bits
Size of FIFOs	16x 8-bit	8x8 bits
Number of transferred data	Up to 65536	Up to 65536
I2S feature	Yes	No

Oct 2024

USB

STM32F373xx

D022691 Rev7

(Jun 2016)

Table 12. Alternate functions for port PA.

Current:

Missing USB mapped on PA11-PA12 as AF14

Expected:

Add USB mapped on PA11-PA12 as AF14.

Apr
2024

STM32G0C1xC

/xE

DS13564 Rev4

(Dec 2022)

3.26 Universal serial bus device (USB) and host (USBH)

Expected:

Add this note:

On the STM32G0C1Kx device, only HSE external source clock is available (HSE bypass)

Sep 2024

Package information

STM32F405xx STM32F407xx

DS8626 Rev9

(Aug 2020)

Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

Current:

Table name: UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

Expected:

Table name:

UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)

Mar 2024

STM32H523xx

(April 2024)

6.9 UFBGA144 package information (A0Y2)

Current :

6.9 UFBGA144 package information (A0Y2)

Expected :

The package code for UFBGA144 = A02Y (not A0Y2)

The section title should be: 6.9 UFBGA144 package information (A02Y)

Oct 2024

STM32WL5MOC

DS14084 Rev4 (February 2024)

6.2 LGA92 package information

Current:

6.2 LGA92 package information

Expected

6.2 LGA92 package information (B0HB)

Oct 2024

Application circuits

STM32WL33xx

(Jun 2024)

Figure 12. STM32WL33xx application circuit with SMPS, VFQFPN48 package

Expected:

Add new line with C49 and C50.

Description: Decoupling capacitor for PA VDD pin

Sep 2024

Document

Title

STM32WL33xx