Issue is that:
ETH->DMACTDRLR, // Channel Tx descriptor ring length register (ETH_DMACTXRLR)
ETH_DMACTDRLR_TDRL
opened a bug:
https://github.com/STMicroelectronics/STM32CubeH7/issues/198
current description:
TDRL[9:0]: Transmit Descriptor Ring Length
This field sets the maximum number of Tx descriptors in the circular descriptor ring. The
maximum number of descriptors is limited to 1K descriptors. It is recommended to put a
minimum ring descriptor length of 4.
!!!!!!!!!!!!!!!!!!!!!!!!
But in reality you should put NUMBER_OF_TX_DESCRIPTORS - 1 (MINUS ONE)
!!!!!!!!!!!!!!!!!!!!!!!!
HELP!
I have ring buffer of length 5.
ETH code is running on M4 core.
5 items transmit without issues.
During 5th item transmission I set tail to be 1st item in ring buffer.
After transmission is over ETH->DMACCATDR register points to element after 5th.
// [0] <- I set this as tail when transmitting 5th element
// [1]
// [2]
// [3]
// [4] <- current 5th item being transmitted AND (DMACCATDR) before transmitting 5th item
// [X]
No matter what I set in tail, 6 packet (which is now 1st in ring buffer) is never transmitted. I tried setting tail element 0, 1, 2, 3 ,4, outside buffer element 5 or 6.
// [0] <- current 6th item being transmitted
// [1] <- I set this as tail when transmitting 6th element
// [2]
// [3]
// [4]
// [X] <- (DMACCATDR) before transmitting 6th element
Documentation "RM0399 Reference manual" states:
// The DMA automatically wraps around the base address when the end of ring is reached, as
// shown in Figure 841: DMA descriptor ring.
DMACTDRLR = 5
DMACSR = 0x0000c404 (NIS, AIS, ETI, TBU)
