Ask questions and find answers on STM32 microprocessors, including hardware, power, DRAM, flashing, interfacing, device tree, and peripherals.
Hi,Suppose I have an I3C target endpoint sending Hot-join request after RSTDAA, is STM32H562/3ZI capable of detecting the Hot-join and pass it on to the firmware layer ? I see Hot-join request support and sample code as an I3C Target in STM32Cube rep...
Hi,I am trying to boot an STM32MP257F with M33 master from SD-card (BOOT=0111).I get the following error on PH4:----------------------------------------blockingfailureS-0002031104084FFCNS-0000000000000000L-000000AE------------------------------------...
I am trying to Generate a periodic interrupts using TIMERS in STM32mp257f how should I proceed? In timer openstlinux drivers there is no specific driver mentioned for periodic interrupts? How can I achieve this?
Im trying to add firefox to the Yocto distribution package provided by STI have addded meta-clang, meta-rust, meta-lts-mixins, meta-browser/meta-firefox, meta-openembeddedFirefox needs x11 dependencies so i added x11 depds as explained by this wiki p...
Hi all,I'm working on a custom STM32MP135 SOC hosting a MMC memory.The barebone firmware creates some tasks by the osThreadNew() function and works correctly.Now I'm inserting FATFs module (moving from FileX) on the firmware to support the FAT fs on ...
Hello,I was able to make the SDL2 library works with KMSDRM with kernel 5.15 Kirkston but with kernel 6.6 Scarthgap it doesn't work. I also configured the kmsdrm to work in the .bbappend file since I am using Yocto. I can see from the log.configure t...
Hi,We use the USB OTG controller in host mode with its internal FS PHY.Our DT node is the following:&i2c4 { ... pmic: stpmic@33 { compatible = "st,stpmic1"; ... regulators { compatible = "st,stpmic1-regulators"; ...
Hello,Currently I'm working on a project that requires a synchronized clock signal between multiple devices connected through Ethernet.The logic solution for this is PTP, and using linuxptp I was able to archive synchronous PPS on PG8 pin between dev...
Hello,We are currently working with the STM32MP257F-DK development board and encountered an unexpected behavior while accessing the Ethernet DMA Mode Register (ETH_DMAMR), located at address offset 0x1000 as per section 92.11.2 of the reference manua...
I'm using a custom board, and use the optee device tree generated by STM32CUBEMX and full UART log. Panic at core/kernel/dt_driver.c:904 <probe_dt_drivers>. How to solve this problem?
