Observation on ETH_DMAMR Register Behavior on STM32MP257F-DK Board

[Aks]

Hello,

We are currently working with the STM32MP257F-DK development board and encountered an unexpected behavior while accessing the Ethernet DMA Mode Register (ETH_DMAMR), located at address offset 0x1000 as per section 92.11.2 of the reference manual.

According to the documentation, the reset value of this register should be 0x00000000. In particular, Bit 0 (SWR: Software Reset) is defined to be cleared (0) after the reset operation is completed.

However, upon reading this register after system initialization, we consistently observe the value 0x00000001, indicating that the SWR bit remains set. This suggests the software reset is still ongoing or not completed, which is contrary to the expected default state after a successful system boot.
We have verified that all required PHY clocks and Ethernet clocks are active .

Could you please advise if this is a known behavior or if there are additional initialization requirements that need to be met to ensure proper reset deassertion?

Best regards,
Akshitha pattem

[PatrickF · Accepted solution]

Hi,

this probably seen when the ETH GMAC miss some clocks from the RCC or the PHY.

Did you enable and configure it correctly ?

Please check that the device tree is aligned with the HW . For STM32MP257F-DK, I think it should be https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY--CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29_is_provided_by_a_Phy_Crystal-29

Regards