STM32MP157 PTP Flex pps drift

[HReis.1]

Hello,

Currently I'm working on a project that requires a synchronized clock signal between multiple devices connected through Ethernet.

The logic solution for this is PTP, and using linuxptp I was able to archive synchronous PPS on PG8 pin between devices with a jitter smaller than 1us for 1Hz. 

Now the problem is that the requirement for PPS frequency is not 1Hz but a OR between a 100Hz and 1.25Hz (see attached image). From documentation, flexible PPS output may be the solution and started testing it by generating the 100Hz signal. Here is were I found the issue, after program PPSCMD[3:0] with start I notice that the 100Hz signal starts to drift slowly (around 20us/s).

Now strange part is if I use fixed PPS (bit PPSEN0 of MACPPSCR cleared) with any frequency (1Hz to 16kHz with digital rollover) there is  no drift. From my understanding the reference clock for pps is the same as system time thus adjusted by ptp protocol for maintaining synchronization.

Is my assumption correct or when flex pps is enabled a different reference clock is selected?

Best regards

[GatienC]

Hello,

I think I encountered the same behavior when investigating something else. I think I even saw a drift of the PPS signal with fixed PPS. I haven't had the time to investigate this but I will be getting back to it.

For now, maybe some hints that may lead you on the right track:

1) Check if the clock source is an oscillator subject to variations (internal oscillator).

2) Do you have another board you can link to yours and run PTP synchronization between them to compare PPS outputs to see if they both drift using flexible PPS?

3) Can you try to generate different flexible PPS signals to see if the frequency impacts the drift please?

Best regards,

Gatien

[HReis.1]

Hello,

I'm back on this project, what I found out is when using flexible pps, target time registers are only compared with system time for the first pulse. This means that a single pulse will always occur at the time specified on target time register with width specified by ETH_MACPPSWR. When using pulse train the same applies but only for the first pulse the remaining pulses are generated by adding ETH_MACPPSIR value and no more comparisons with system time are made.

That is why the drift occurs (at least is what I think) and to mitigate this problem I'm trying to use single pulse with interrupt. On interrupt handler, the next pulse is then configured. The problem that I'm getting with this solution is that the interrupt occurs inside pulse and as target time registers are being updated this seams to be interfering with the periodicity of the pulses.

[Warlord]

Hello,

  I do confirm that there is a slight drift in PPS-output while using flexible PPS generator. I need a 0.25Hz frequency. Two devices, master and slave. If I setup master and slave PPS registers only once - it goes in-sync, at least for 5 minutes. If I do re-setup master or slave - the time gap of about 1us appears.