STM32H7 FDCAN clock issue

[Mr_M_from_G]

Hello all,

I have trouble running FDCAN on an STM32H742VG rev V when the cpu clock is above 300 MHz.

I have

D1CPRE = DIV1

HPRE = DIV2

D2PPRE1= DIV2

leading to the maximum allowed APB1 peripheral clock (= fdcan_pclk) for cpu clock >= 300 MHz (75 MHz for cpu clk = 300 MHz)

also I have HSE = 24 MHz used as FDCAN clk (= fdcan_ker_ck) and with FDCAN_CCU_CCFG.BCC = 1 and FDCAN_CCU_CCFG.CDIV=0 this is also fdcan_tq_clk and so fdcan_tq_clk is always smaller than fdcan_pclk.

But still this configuration only runs stable up to 300 MHz, at 330 MHz it fails after about a minute and with 360 MHz and above it does not work at all.

I have no trouble running UARTs, SPI, timers, ADC, DAC with cpu clk = 480 MHz, its only the FDCAN.

Did I miss something? Any known issues or workarounds?

Thanks for any hint

Martin

[nukersson]

After your advice and some investigation I found out - it could be solved by using LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_HSE) instead of LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q)

Here may be a drawback: depending on HSE frequency FDCAN may be needed properly configured.

[nukersson]

Ok Setting PLL1 properly shall work:

Just change DIV1Q from 2 to 8 or some else value s.t. PLL1Q source for FDCAN provides appropirate clock signal (in my case 120MHz)

Please refer also to this solution for more information: https://community.st.com/t5/stm32cubemx-mcus/stm32h745-fdcan-clock-frequency/td-p/83540