Ok Setting PLL1 properly shall work:Just change DIV1Q from 2 to 8 or some else value s.t. PLL1Q source for FDCAN provides appropirate clock signal (in my case 120MHz) Please refer also to this solution for more information: https://community.st.com/t...

After your advice and some investigation I found out - it could be solved by using LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_HSE) instead of LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q)Here may be a drawback: depending on HSE freq...

I can confirm it. On my MB1363-NUCLEO-H745ZI-Q-C01 it works with SYSCLK=96MHz and does not work with SYSCLK=480MHz