STM32 MPUs Products

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Resolved! About the SRAM4 access size from M4 and A7 cores

Many thanks for your help!Currently, we are using the SRAM4 memory as a shared RAM mapped between the M4 and the A7 cores. We have a Linux application that writes full 32bit values from the A7 core, as in the following snippet: *(volatile uint32_t...

Resolved! OP-TEE RNG Oddity

Hello,Sorry for a long post this needs some context.I've been configuring and testing OP-TEE from the following guide:https://wiki.st.com/stm32mpu/wiki/How_to_configure_OP-TEEI'm using the STMicro fork of optee_os (tag 3.16.0-stm32mp-r2), and the OP-...

Macdog by Associate III
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  • 14 replies
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How to use boot pin as gpio

Hi, I use boot1 pin as gpio key function. The boot1 is PI5, and I configure it in kernel dts code. When the system boot up, the input event0 device is shows, but I use hexdump can not get any key code data. Currently, my board is boot from sdcard. gp...

SChen.19 by Associate II
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  • 2 replies
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STM32MP151. Display controller questions.

1. Can the display interface be driven by the M4 core while the A7 core is powered down?1a. Can the AXI interconnect peripherals be driven by the M4 while the A7 cores are powered down?2. Display controller - is there any loss in performance if using...

BReib.1 by Associate
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  • 1 replies
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Resolved! TF-A boot fails for FSBL [Solved]

Hi all,I updated my project from Morty (2.2) to Kirkstone (4.1). After doing the required fixes/updates on the recipes, I have problems booting the FSBL. I am using the Cube Programmer to flash the image. Below is the log:STM32CubeProgrammer API v2.1...

vfranchi by Associate III
  • 6219 Views
  • 23 replies
  • 0 kudos