2022-04-26 07:00 AM
It fails when called by `HAL_ADC_Start_DMA(&hadc2, &ADCbuf[0], 1)` exact position is at stm32h7xx_hal_adc.c `ADC_Enable()` depicted in the picture below. I have no idea why this happening. Called by itself an internal error!
And complete project has been attached.
And pcb layout:
Solved! Go to Solution.
2022-04-27 06:16 AM
It seems we have hardware bug mentioned here:
I will test ans report. Test report:
CubeIDE does not generate hadc2.Init.ClockPrescaler= .
Then I've added folloing line to `MX_ADC_Init()` function before `HAL_ADC_Init(&hadc2)`:
hadc2.Init.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4;
And all ASYNC prescaler prevent ADC for being enabled.
And the ADC got started, but why?
Could some employee please report this bug?
2022-04-26 07:02 AM
I've forgot to add ADC and stm32h7 and HAL to flag, I ask if employee's could do this.
2022-04-26 08:45 AM
Ensure the ADC clock mux is set to the correct value and that the clock is being enabled. CubeMX has a bug where this doesn't happen sometimes.
2022-04-26 03:25 PM
You can edit those tags yourself with clicking "Edit Topics" option in the same menu where you edit contents of the post.
Does the VDDA/VREF+ has the necessary capacitors and VCC3.3 some bigger with several uF?
2022-04-26 05:37 PM
@SeyyedMohammad Is your MCU H743 or H750VB as on the schema?
If the 750, is it by chance stepping Y? There's a difference in ADC behavior and errata for stepping Y.
2022-04-26 10:05 PM
No H743 is, but what is meaning stepping Y?
2022-04-26 10:23 PM
So wierdly ADC clock mux is grayed out in clock distribution gui and I think this is a bug*. but I've checked the register ADCSEL in Reference manual, named in cubeide as ADCSRC (another deficiet*) has correctly selected 00 means PLL2P.
2022-04-26 10:28 PM
As you can see VREF/VDDA has no cap on this chinees board, but VCC3.3 has also 22u.
2022-04-27 12:39 AM
I've added 0.1u 1u cap to VDDA/Vref+ but no thing changed.
2022-04-27 01:57 AM
I've added 0.1u 1u cap to VDDA/Vref+ but no thing changed.