Strange behavior PLLI2SDIVR on STM32F413. Where is my mistake?

[kv193]

I have init PLL2 (PLLI2S) for f = 24.576 MHz. Then for at MCO2 pin there is clock 12.288 MHz (controled by oscillogaph, it is true). After thar I setup PLLI2SDIV2 = 12 and think view at MCK_A (SAI1) 2.048 MHz. But view 1.89 MHz. Then I try PLLI2SDIV2 = 11 and get exactly 2.048 MHz. This behavior is not as in "Reference Manual STM32F413" p.175.

Where is my mistake?

[waclawek.jan]

> After thar I setup PLLI2SDIV2 = 12

How?

Read out and post content of relevant registers.

JW

[kv193]

Code fragment:

RCC->DCKCFGR = 0b00000000000000000000001000001100;

       /* | |||||||||  |||||||  +++++-- PLLI2SDIVR = 12

        * | |||||||||  ||+++++----------- PLLDIVR  = 1

        * | |||||||||  |+---------------- CKDFSDM2ASEL

        * | |||||||||  +----------------- CKDFSDM1ASEL

        * | |||||||++---------------------- SAI1ASRC 00 - PLLI2S_R divided (R2)

        * | |||||++------------------------ SAI1BSRC 00 - PLLI2S_R divided (R2)

        * | ||||+-------------------------- TIMPRE

        * | ||++--------------------------- I2S1SRC

        * | ++----------------------------- I2S2SRC

        * +--------------------------------- CKDFSDMSEL

        */

RCC->CR |= RCC_CR_PLLI2SON;

while ((RCC->CR & RCC_CR_PLLI2SRDY) == 0) {

}

Register contents from debugger:

Oscilogram MCO2:

Oscillogram MCLK_A

May be 1 / k = 1 / (PLLI2SDIVR+1) ?

[waclawek.jan]

Humm...

> May be 1 / k = 1 / (PLLI2SDIVR+1) ?

Looks much like it is, although the documentation says otherwise.

Unfortunately, I don't have a 'F413 to try. In 'F446, there's a similar post-divider between PLLs and SAI clock, and that indeed divides by (value+1):

00000: PLLI2SDIVQ = /1

00001: PLLI2SDIVQ = /2

...

but that of course proves nothing.

@Imen DAHMEN​ , can please the 'F413 RCC_DCKCFGR.PLLI2SDIVR (and perhaps also PLLDIVR) description be checked? Thanks.

JW

[kv193]

Thank you for answer.

STM32 is good product. But there is opinion, that for last 20 years quality of IC and (ecpecialy) docs is come down. And I will be more trust to my eyes and oscilloscopes.

Note: very strange to have different Clock descriptions for chips in same family (STM32F4).

Good luck.

[Imen.D]

Hi @VK.17lochkov​ and @Community member​ ,

Thanks for bringing this issue to my attention.

I will check this and I will informed you about the taken actions, or explanation if needed.

Thanks,

Imen

[waclawek.jan]

Thanks, Imen.

JW