I have init PLL2 (PLLI2S) for f = 24.576 MHz. Then for at MCO2 pin there is clock 12.288 MHz (controled by oscillogaph, it is true). After thar I setup PLLI2SDIV2 = 12 and think view at MCK_A (SAI1) 2.048 MHz. But view 1.89 MHz. Then I try PLLI2SDIV2...