STM32 MCUs Products

When we use the STLINK V3 to connect to the SWD interface of the STM32H563, it keeps showing “target not found”. We tested the waveforms output by the STLINK V3 and found that some SWDIO rising edges almost coincide with the SWCLK rising edges, so even a slight change in the external wiring causes the connection to fail. We suspect that the wiring affects the position of the signal rising edges, leading to sampling errors on SWCLK. Is it possible to adjust the timing of the STLINK V3 so that the time interval between the SWDIO and SWCLK rising edges is widened as much as possible, thereby increasing the system margin?Our STLINK V3 firmware version is V3J17xxxx.

Hi everyone,I'm facing an issue while reading a tactile push button connected to PB15 on an STM32G070 series MCU.The GPIO is configured as an input with an internal pull-up resistor. My expected behavior is:Button not pressed: GPIO reads HIGH (1). Button pressed: GPIO reads LOW (0).However, I'm always getting LOW (0), regardless of whether the button is pressed or released.Here is what I've checked so far: Verified continuity between the button and the MCU pin; it seems fine. Checked the button pin configuration, it looks fine Tried reading the GPIO raw value in code, but it consistently returns 0. I'm not sure whether I'm missing any thingCould anyone suggest what I should check next to debug this issue?I've attached images of the relevant configuration for reference.Thanks in advance for your help! 

What could be the possible reason for the unresponsive feedback button on the production line? The defect rate is about 2% (total of 2000PCS).The circuit diagram is as follows.We conducted a plug-in replacement experiment, and the phenomenon followed the STM32F071CBT6TR.We plan to conduct IV curve experiments on pins 39, 40, and 41 to determine if there are any issues with these pins. Additionally, we suspect that there may be a problem with pin 6. Have you encountered similar phenomena before? Where is the problem usually?

Hello everybodyCould someone provide me with a schematic diagram for connecting an STM32U599NJ to an MT29F16G08ABCCBH1-AAT:C? Thanks a lot. Best regards

I was wondering, despite the 10-year longevity commitment cited on the page of the STM32G0 microcontroller, the STM32G0B0VET6 has basically no more supply worldwide and lead time of more than a year.Is there a reason for that? Should I move to a more “available” microcontroller?

Hello,I am currently developing a USB Device application using the STM32N657L0.I am reaching out to ask for advice because I am having difficulty meeting the target power consumption requirement of 5V, 2mA max during USB Suspend state. Our target conditions and system requirements are as follows:VDDCORE uses an external power supply. The USB Driver must be maintained during USB Suspend. The system must be able to wake up and recover via USB. Power consumption must remain below 5V, 2mA during USB Suspend.Currently, when the chip is configured in STOP Mode, the measured power consumption is:VDDA18AON (1.8V): ~5mA VDDCORE (0.81V): ~40mA We are looking for ways to further reduce these currents to meet the 2mA requirement.Could you please guide us on how to optimize the power modes, clock gating, or power supply configurations to achieve this? Any suggestions or reference guidelines would be greatly appreciated.Thank you for your support.Best regards,

Hello,I am using an STM32N657 on a custom board.I need to use PA6 as PIXCLK, so I would like to move the BOOT1 function from the default PA6 pin to PN10.According to the STM32N6 BootROM/OTP description, I understood that BOOT1 can be remapped using OTP19 (BOOTROM_CONFIG_10): I programmed OTP19 with 0x15200000 in STM32CubeProgrammer to change BOOT1 from PA6 to PN10.Before programming OTP19, I could connect to the MCU normally through ST-LINK/SWD using PA6 as BOOT1.However, after programming OTP19 to 0x15200000, I can no longer connect to the MCU.The same issue has occurred on more than one custom board.My test conditions are:MCU: STM32N657 I/O supply voltage: 1.8 V BOOT1 remapped to: PN10 OTP19 programmed value: 0x15200000 PN10 is held HIGH before and during reset ST-LINK detects the target voltage During connection, STM32CubeProgrammer can sometimes identify Device ID 0x486, but then reports that the connection to device 0x486 is lost The board works and SWD connection is available bef

Hello ST Team,We have a custom STM32N657Z0H3Q board on which BOOT1 is routed to PN10 instead of the default PA6.To configure the Boot ROM to sample BOOT1 from PN10, we programmed OTP Word 19 (BOOTROM_CONFIG_10) as described in RM0486 Rev. 4, Section 5, Table 18:dev_boot_port [24:21] = 9 → Bank N (PN) → 9 << 21 = 0x01200000 dev_boot_pin [28:25] = 10 → Pin 10 → 10 << 25 = 0x14000000 OTP19 = 0x15200000Steps FollowedBefore programming, we read OTP through SWD. OTP19 was 0x00000000, with status 0x00000000, indicating that it was unprogrammed and not write-locked. SWD/ST-LINK access was working normally. We programmed OTP19 with 0x15200000 using STM32CubeProgrammer v2.23.0, without enabling the lock option. The tool reported: "OTP words programming done successfully"   After the next power cycle/reboot, the device no longer enters Development Boot. Instead, it boots from Flash, and our FSBL and application start running normally. SWD/debug access is no longer available.Same

Hello,We are designing a PCB around the STM32N657B0 (VFBGA198) using the internal SMPS. VDDSMPS and VDDA18PMU are fed from a dedicated 1.8 V buck, with VDDA18PMU filtered from the same rail, as per Figure 2 in DS14791.For our derating and fault analysis we need the absolute maximum ratings of these two pins, and we cannot find them in any current ST document:DS14791 Rev 11 (Sep 2026), Table 22 “Voltage characteristics”: no VDDSMPS or VDDA18PMU row. The “VDDA18 – VSS, 1.98 V” row lists only VDDA18PLL, VDDA18CSI, VDDA18USB and VDDA18ADC. DS14791 Rev 11, Table 25 “General operating conditions”: VDDSMPS and VDDA18PMU are 1.62 / 1.8 / 1.89 V. DS14791 Rev 11, Table 29 “Characteristics of SMPS step-down”: the input is called “VDDA18”, 1.62 to 1.89 V. AN5967 Rev 6, AN6000 Rev 1 and RM0486 Rev 4: no absolute maximum for either pin.QuestionsWhat are the absolute maximum ratings (min and max) for VDDSMPS and VDDA18PMU? Does the “VDDA18 – VSS, 1.98 V” row in Table 22 also cover VDDSMPS and VDDA18P

Hello,Our STM32N657 appears to be revision B. We use a battery-powered board with an STM6601 power-button controller. The MCU asserts PSHOLD early in the FSBL to keep power enabled.ES0620, section 2.2.18 specifies setting SYSCFG_CM55RSTCR.CORE_RESET_TYPE, followed by a software reset (NVIC_SystemReset()), after the first power-on reset.That additional reset conflicts with our power-hold arrangement.Is the initial software reset strictly required for the NRST workaround, or can we set CORE_RESET_TYPE and continue booting? If it is mandatory, is there a supported alternative that avoids this extra reset?Thanks!

Subject: STM32F373CCT6 SDADC: Wrong Readings with VDDA Reference on One Board After Environmental TestingHello ST Support Team,We use the STM32F373CCT6 to read four analog inputs with SDADC1 and SDADC2. One of our boards developed a problem during environmental testing (temperature change, dry heat, cold, damp heat cyclic and steady state), where it ran in full-function mode throughout.What happenedThe board worked correctly until day 2 of the damp heat steady-state test (40 °C). Then all four channels read with an offset (for example, a 100 V input read as 50 V). After a power cycle it worked for 2 to 3 hours, then read full scale (3.3 V) even with no input. Reflashing the firmware did not help.A couple of days later we debugged it with the same firmware (internal VDDA reference). With no input, each channel should read 1.65 V (confirmed with a multimeter at the MCU pin), but the firmware reads 1.85 V on all four channels. With the reference set to internal 1.8 V, the readings are cor

HI,I am working on a board using STM32H573V and have a working solution with UCPD detecting an inserted memory stick and running the MSC class. In an other part of the software I am using PC9 as an GPIO push-pull, low speed output and as soon as I set it to high, the voltage at PB14 (UCPD CC2) drops from 3.3V to 1.5V and my UCPD handler signals a device attached and turns VBUS on even though nothing is attached. There is no other electrical connection between PC9 and PB14 on the board. I am using a TCPP03-M20 for VBUS switching. The board is acting as VBUS source.

Hi everyone, I am encountering an issue with the STM32G0B1RCTB microcontroller, specifically related to the "errata" concerning its dual-bank memory architecture.My project uses firmware structured as follows: a bootloader located at the beginning of the flash (0x08000000), an application located at 0x08006000, and a CRC data section—generated during the post-build process to ensure firmware integrity—placed at the end of the flash (0x0803F000).I need to keep the prefetch feature enabled; however, due to a known issue inherent to this microcontroller, the system crashes once the firmware exceeds a certain size.To resolve this, I decided to modify the option bytes to set the device to "single-bank" mode, which would allow me to keep the prefetch feature enabled.However, when the microcontroller resets (triggered by `FLASH->CR |= FLASH_CR_OBL_LAUNCH;`) to apply the new option bytes, the bootloader executes correctly (as it is located at the start of the flash), but the jump to the app

Page 47 Figure 15. GND Plane: GND plan instead of GND planeGuidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs - Application note Can’t attach a screenshot for some reason

Hello,I am using NUCLEO-U5A5ZJ-Q evaluation board.I have configured ADC1 to do a single conversion and a software start.I want to measure ADC conversion time.My main test code looks like thiswhile(1){    HAL_ADC_Start_IT(&hadc1);            HAL_Delay(1);            HAL_ADC_Stop_IT(&hadc1);    adc_value = hadc1.Instance->DR;    }I have added a test pin for debugging. To check with oscilloscope.I set pin high inside HAL_ADC_Start_IT just before ADC enabled.And I reset pin inside interrupt procedure ADC1_2_IRQHandler.I have connected oscilloscope to ADC input pin directly to see sample begin. As ADC capacitor is connected to input and it has some chargeit is possible to see discharge curve on the screen.Here is the picture. Yellow shows time between start and end of sampling.Blue shows sampling begin (when capacitor is connected).Why there are two discharge curves?I have configured to do only one sample.Also the timing is wrong.I am using clock from external HSE.It is 16MHZ. Di

I am into configuring a STM32H750VBT6 and I want to configure ETMv4 inside the code of the program and my objective is to detect and capture data on 5 trace pins.I configured all trace pipeline including, CSTF,ETF,ETM,DWT and TPIU. also I considered opening Locks, enabling TRCENA in CoreDebug_:DEMCR and enabling required clock domains in DBGMCU_CR.After all I am just sighting clock signal on TRACECLK pin. I also checked TPIU unit if it successfully outputs test patterns like AA55 and FF00. Test patterns worked properly but when disabling test pattern only clock comes out through the trace pins.I am looking for someone who configured that before to help me prevail it.here are my functions:#include "ETMv4.h"#include "core_cm7.h"uint32_t startAddr = 0;uint32_t stopAddr = 0;void Parallel_Trace_configure(){ TraceGPIO_Configure(); Disable_ETM(); TPIU_Configure(); ETF_Configure(); CSTF_Configure(); ETM_Configure(); SetupStartStopAddr(); DWT_Configure(); Enable_ETM();}void TPIU_Config

Subject: STM32N657X0H3Q Power Sequence Deviation – Impact on Reliability and OperationHello,I am designing a custom board based on the STM32N657X0H3Q, using the STM32N6570-DK as a reference. The MCU is configured to use the internal SMPS for VCORE generation.Unfortunately, my design does not fully comply with the recommended power sequencing described in the documentation:The various 1.8 V rails are generated from a single DC/DC converter. VDDA18USB, VDDA18CSI, and VDDA18ADC are powered directly from this 1.8 V rail. These rails are not gated by PWR_ON and therefore may become valid before or simultaneously with the PWR_ON assertion.The MCU appears to boot and operate correctly during initial testing, but I would like to understand the implications of this deviation from the recommended power sequence.My questions are:Does powering VDDA18USB, VDDA18CSI, and VDDA18ADC before (or independently of) PWR_ON create any risk of device damage or reduced reliability? Are there any known functio

When TxRSTU and RETRIG are enabled with CONT disabled, will the timer still trigger a register update when it's counter reaches it's PER value? Since it says in the image below that the PER event is generated but says it re-starts from 0 when it's reset but doesn't mention roll-over, and the image above says it'll update registers on timer reset and rollover. Essentially what I'm asking is does it count as a roll-over when the timer reaches its period value when CONT=0? Since I need to know if it'll update it's registers at the end of it's period or no.Any help is much appreciated :) 

Could I get the reference circuit for the STM32G474MET?

Hello,Does anyone have any information about the current availability of the STM32H573RIT6 microcontroller?I've been checking major distributors such as Mouser, DigiKey, Farnell, and TME, but this particular MCU seems to be completely unavailable.Some distributors are showing very long lead times, with expected deliveries in 2027.I'm currently designing a new device based on this MCU, and I'm concerned about its availability, especially for future production.Does anyone know why the STM32H573RIT6 is so difficult to obtain?Is this a temporary supply issue, or are there any production problems or changes planned for this specific part number?I would really appreciate any information, especially from someone at STMicroelectronics.Thank you!

I’ve tried to include the ITCM for a while w/o sucess only getting a few cells cooperating leaving the lions share as ???????? in the memory view (STM32CubeIDE 2.2.0). Notably, the DTCM works fine after initiation. I start out (from reset) to verify the ICTMCR/DTCMCR as enabled, identifying the size as 256KB (both).After this I blindly writes 0 (32-bit) all over the place, this makes a very few ITCM cells 0x00000000.If I only initiates DTCM, a few ITCM cells become visible but what looks like randomized not 0.As stated earlier the full DTCM is now 0x00000000. The DBGMCU_IDC isDevID:0x499RevID:0x2000 Somebody sees what I’m doing wrong?All help appreciated!/Henrik  

Hi everyone, I’m working with a custom made STM32F446ZET6 board that otherwise functions perfectly (all peripherals, flash programming, etc. work fine). The only thing that doesn’t is the ROM bootloader. I can’t get USB DFU or UART boot to respond no matter what I do. What I’ve verified BOOT0 = 1 (3.3 V) at reset NRST pulled high, no reset loops VDDUSB = 3.3 V, decoupled with 100 nF HSE = Abracon ABLS-8 MHz-12 pF, started with 18 pF load caps and lowered to 10 pF as I saw in a post here this might be the cause PA9 connected directly to VBUS (5 V)  PA11/PA12 wired to USB-FS D−/D+ (verified routing and continuity) Board runs normal firmware from Flash with no issues What I’ve tried BOOT0=1, reset → USB never enumerates Tried UART boot (PA10 RX, PA9 TX, 115200 8E1) → no ACK, completely silent. Verified with ST-Link under reset: RDP = 0xAA (no protection) MEMRMP = 0x0, VTOR = 0x0 → seems like it’s still mapping main Flash, not System Memory. Jum

I am looking at the datasheet and reference manual for the STM32H750. I am trying to learn about the connections between buses and I saw on the reference manual that AHB2 in the D2 domain has no master bus port, however the datasheet shows an AHB/APB bridge between buses labeled AHB2 and APB2. later in section 2.1.3 of the reference manual, there is no mention of an AHB2 to APB2 connection. What does this mean for accessing peripherals on the AHP2 peripheral bus, is it intended for AHB1 as per the reference manual, or through AHB2 as per the datasheet, or is there another way I am not seeing?Reference manual Diagram showing no AHB2 → APB2 connectionDatasheet Block Diagram showing APB2 connection to AHB2 through AHB/APB bus bridge (blue box) 

Hi,I'm trying to program a blank STM32H573 through the embedded system bootloader over I2C4, but the bootloader does not respond.SetupBlank flash, product state Open, BOOT0 = 1 (measured at the MCU pin), board power-cycled Host: Aardvark I2C master at 100 kHz, address 0x65 (per AN2606) No debugger, USB or UART connectedResultLines idle high, but 0x65 is NACKed A full scan from 0x00 to 0x7F gets no ACKQuestionsAN2606 lists I2C4 on PD12/PD13. Does the bootloader use only those pins, or also other I2C4 pins such as PB8/PB9? Is BOOT0 = 1 enough on a blank device, or is STiROT involved in this boot path?Thanks.

Page 31 of AN5093, AN2687 is mentioned while discussing crystals. AN2687 is about a LCD software driver. I believe they meant to mention AN2867 which is also mentioned earlier in the document.