STM32 MCUs

When using an STM32 timer to control LED brightness, is it generally better to keep the timer period fixed and adjust the compare value, rather than changing the timer period as well?My understanding is that changing the compare value allows the duty cycle to vary while keeping the PWM frequency constant. Are there any practical considerations when selecting the timer prescaler and auto-reload value, particularly when aiming for smooth dimming across the full brightness range?I’d appreciate any guidance on the timer configuration and potential trade-offs.

I'm looking into the best way to control the brightness of an LED load using PWM from an STM32 and would appreciate some advice on the practical side of the implementation.My understanding is that the average brightness can be controlled by changing the PWM duty cycle while keeping the LED supply voltage constant. For example, increasing the duty cycle should increase the average current and therefore the perceived brightness.What I'm less certain about is choosing an appropriate PWM frequency. A very low frequency could potentially result in visible flicker, while a much higher frequency increases the number of switching events.For a longer LED load, I'm also wondering whether it is better to keep the STM32 PWM output isolated from the actual LED current path using a dedicated MOSFET or LED driver.If anyone has implemented PWM-controlled LED lighting with an STM32, what PWM frequency and timer configuration have you found to be a good starting point?I'm particularly interested in the

I am working on stm32 C5A3ZG platform for one of my projects. I want to use SD card for data logging. I have working SD card module. I tried to use it with nucleo_c5a3zg board using zephyr RTOS and there infrastructure of file management that code is not working on this C5 controller which uses HAL2 driver. It works on other STM32 controllers which use HAL driver.I tried to create a project in STM32CubeMX2 but couldn’t find configuration for SDMMC over SPI which would be required to interface SD card.I checked in STM example library https://dev.st.com/stm32-example-library/result?filters=N4IgpgHghgtgDgGzAOVmEAuA2gXQDQgwDGArpliAMoAqAsgMwBMAwgKwj4gBGA9lAE4ATcpxgBLQYKQB3AemyjSAEX5iAbmH4iCvAYIAKUIgGsoAc3m4Cg1Rv7UAnnEs4AvkA but was not able to find any sample or SD card.Can someone provide a sample code to me otherwise i have to look for potentially changing the platform and move to some other controller.

Hi all,I'm recording 16 kHz mono audio from the on-board digital MEMS mic (MP23DB01HP) of the STM32N6570-DK using the BSP's MDF path (MDF1, filter 0, PE2 MDF1_CCK0, PE8 MDF1_DATIN0, GPDMA1 channel 0, SPI mode, falling edge). The recording runs next to a camera/ISP pipeline, an NPU model and an H.264 encoder, so I want the audio path to cost as little CPU as possible and sound clean.Current setup (BSP defaults for 16 kHz)Kernel clock: IC8 from PLL4 = 50 MHz (HSI-based), PROCDIV = 2, CCKDIV = 12, so the PDM clock is about 2.08 MHz CIC: Sinc4, R = 32; reshape filter on, ÷4 (total decimation 128) Gain +2 (about +6 dB); HPF 0.000625 × fPCM (about 10 Hz) Async continuous acquisition, circular DMA into a 16 KB bufferWhat I triedI built a test firmware that records one clip per MDF configuration (5 s each, one config per boot) and compared them offline. Configs: Sinc4 vs Sinc5 R = 32 (gain steps −7, −8, −9), HPF at 10, 20, 40 and 152 Hz, a PLL4 retune to 81.92 MHz with IC8 ÷ 10 for an exact 2.

Greetings,I am working with nucleo_c5a3zg board and I am using zephyr RTOS for my project. I wanted to interface the sd card and try to do some data logging. I had a adafruit data logger shield which can fit on nucleo_c5a3zg board and there is a shield support in zephyr. When i build and uploaded the code i am getting a error that CMD8 is not supported. During debugging i found out that there is no state change on MISO line. Just to check if my code is wrong i tried same code with nucleo_f446re board and it works fine.Following is the capture from saleae loggic for necleo_c5a3zg board. I can provide other details like code, .dts file, etc.If someone can help me solve this issue it would be much appreciated.

hi guys  I need to put a F/W program on my board that my coworker made but there’s a problem with CN6 so I have to use TAGand I can’t use USE port for power so I can use only VIN  when I was using the STM32CubeProgrammer then I got this error I changed mode, reset mode and frequency but it couldn’t help Does any body know to solve this problem? please let me know 

Hello everyone,I measure a voltage on a STM32L496 using the internal ADC and found the following issue:Setup:The voltage is scaled down via a high-impedance voltage divider (2 x 470kOhm). To avoid distortion by sampling, the voltage divider has a 100nF capacitor. Thus, the capacitive load while sampling is low and the breakdown is 1/20000 → i.e. way lower than the ADC’s resolution. So I do not have to care about source impedance limitations as described in the datasheet (Maximum ADC RAIN).Other data:VREF=VDDA=3.3V (stable) Voltage range of ADC input signal: 0 - 3V (never >3.3V)Effect:I experience a large voltage breakdown when I configure the ADC, via CubeMX generated function MX_ADC3_Init (same happens when I use ADC1). I found, that within MX_ADC3_Init the channel gets configured and the ADC sequencer register ADC_SQR1 is set (I only sample that one channel with the high-impedance voltage divider). As soon as ADC_SQR1 is set, the voltage breaks down, from anything >2.5V to appr

ETH is obviously a dual-clock peripheral, and some of the registers are most probably behind a synchronizer, in the MII clock domain. It’s not unlikely that reading some of those registers imposes waitstates. Writing may not, but then those are subject to the Successive write operations to the same register might not be fully taken into account erratum (which hints at the fact that there’s a 4-MII-clock synchronization mechanism, at least for writing).Can ST confirm or deny, whether reading and/or writing ETH registers imposes waitstates, and in case of yes, can ST please list related registers and also quantify number of waitstates. Here’s why.In particular, we need this to be quantified for the ‘F4xx, but for other families it would be a bonus to have this, too.Thanks,JW

Hi, Folks.I’m using a board with NUN code ending in $CR1, C260400252, MB...Q-C02 if that includes useful rev info.I started powering this ST Nucleo board with +12 from a bench supply, limited at 600 mA, into CN3 pin 24 with ground on pin 20 (19,20,22 all ground) and that was being regulated down to +5 by U25 just fine.  So I let the board see the +5 by inserting CN9:5-6 jumper.With nothing plugged in but power, LD1 was on (green), LD9 red on and green flashing, LD4 red on faintly, LD5 flashing red.  All this as expected except the state of LD9 which appeared to be due to 3V3_STLK existing (regulated from 5V) but no USB connection.  I checked and recorded all the voltages on CN2; everything looked reasonable except pins 9 and 10 pertaining to the internal SMPS which is free floating, because by default VDD1V8 is not being generated (low nonzero voltage at TP14).I was about to plug the cable I’d made into CN1 when I noticed LD5 had stopped flashing and the current being drawn from my 12V

Hi,We’re using an STM32U5G9 with a MIPI DSI panel (driven by the LTDC through the DSI host). The panel is 800×600 and scans in landscape, but it’s mounted rotated, so the user sees a 600×800 portrait image. The panel controller can’t swap its scan direction; the manufacturer confirmed that only X/Y flips are supported.Current pipeline: JPEG frames arrive over the network. The hardware JPEG codec decodes them in bands of about 32 lines, and DMA2D converts each band (YCbCr → RGB888) straight into a single framebuffer that the LTDC scans. There’s no double buffering, because of RAM: the framebuffer alone is about 1.4 MB. Today the server sends frames already rotated to panel orientation.Goal: a framebuffer in the logical (portrait, 600×800) orientation. We could then implement scrolling by remapping lines with the GFXMMU (a ring buffer), and only decode the newly exposed lines.Questions:Can the LTDC or the GFXMMU present a 90°-rotated view of a framebuffer to the panel, without any interm

Hi everyone,We are facing an issue with the RTC on our custom hardware based on the STM32N655X0 MCU and would appreciate any suggestions to help us identify the root cause.1. Project OverviewWe have configured the RTC in our application, and maintaining the correct time across power cycles is an important project requirement.Our firmware is stored in external flash. During development, we use J-Link for programming, and we have also implemented firmware flashing through USB using an FSBL with DFU support.Both flashing methods work successfully. However, we have observed unexpected RTC behaviour after flashing and subsequent power cycles.2. Issue DescriptionAfter flashing the firmware, if we remove the main supply (VDD) and power the board back on after a few minutes, the RTC does not account for the elapsed time correctly.For example, if flashing completes at 12:25 PM and we power off the board immediately, then power it back on at 12:30 PM, the RTC does not reflect the five-minute int

I’ve tried to include the ITCM for a while w/o sucess only getting a few cells cooperating leaving the lions share as ???????? in the memory view (STM32CubeIDE 2.2.0). Notably, the DTCM works fine after initiation. I start out (from reset) to verify the ICTMCR/DTCMCR as enabled, identifying the size as 256KB (both).After this I blindly writes 0 (32-bit) all over the place, this makes a very few ITCM cells 0x00000000.If I only initiates DTCM, a few ITCM cells become visible but what looks like randomized not 0.As stated earlier the full DTCM is now 0x00000000. The DBGMCU_IDC isDevID:0x499RevID:0x2000 Somebody sees what I’m doing wrong?All help appreciated!/Henrik  

Hi,I have this toolchain and need to generate a SBOM:STM IDE v1.18STM IDE GNU Tools for STM32 13.3.Rel1STM32Cube FW_L4 V1.18.1, specified in `\*.ioc` fileSTM32_USB_Device_Library (v2.0_Cube)STM32CubeMX 6.14.0FreeRTOS (10.3.1)How could I turn this into a SBOM?I tried scanning the folder strucutre with syft but this did not work. I then tried to manually make a syft Json file, but when testing for vulnerabiliteies (like e.g. here ) i could not find them. I am not sure how to specify the above components, such that they get recognized by the automated search engine (Grype).I found a statement from ST, that SBOMs will be provided for their products, but I could not find said lists for my toolchain. Some repositories on the GitHub Repositores contain `sbom_cdx.json`. However, I struggle to connect my Toolchain components to the repositories on Github (there are over 700 and for example "stm32cubeIDE" returns 0). Any help is appreciated! Related Links:Wikip

Dear all,I am using an application on the NUCLEO-F401RE board. I wrote and successfully compiled a program (with no errors), but I am encountering an error during debugging with the message: "Failed to execute MI command: remote target localhost:61234".The ST-LINK (ST-LINK GDB server) is configured as the debug probe and SWD interface.I have replaced the communication cables and reinstalled the STM32CubeIDE software. It used to work normally.The log is attached below:

Hello,I am evaluating cryptographic performance for a secure boot using a NUCLEO-H533RE board and the OEMiRoT example from STM32CubeH5.I compared two AES-128-CTR implementations:Software: mbedtls_aes_crypt_ctr(). Hardware-backed: bootutil_aes_ctr_encrypt() using SAES.The mean encryption times are:Input size Software SAES-backed implementation 32 bytes 10.55 µs 29.46 µs 256 bytes 76.70 µs 222.88 µs 1024 bytes 303.50 µs 886.02 µs  For an academic comparison, is it accurate to describe this result as “software AES-CTR versus SAES ECB with software CTR and driver protection overhead”? Thank you!