STM32CubeMX (MCUs)

i am using cube mx version 6.18.0and cube ide v2.2.0my question is is there a  way to create a new project from an already existing ioc filei don’t want to do all the ioc setting all over again, it will take like hours to do all the settings. 

User labels for handle structure In STM32CubeMX, the user can define a User Label for GPIO pins.For example:  User Label: LED_REDThis generates:#define LED_RED_Pin GPIO_PIN_5#define LED_RED_GPIO_Port GPIOAHowever, there is no User Label option for handle structures.For example:extern I2C_HandleTypeDef hi2c;extern TIM_HandleTypeDef htim2;extern ADC_HandleTypeDef hadc1;extern UART_HandleTypeDef huart1;Is would be nice to have al user label for a uart, so the application source can refer to that user label. For example:extern UART_HandleTypeDef MY_COM_huart;extern TIM_HandleTypeDef LED_RED_htim;Thanks,

I’m just getting started with Cube MX and IDE. (MX: 6.18.1, IDE:2.2.0, Debian Trixie platform)I have the Nucleo-144 board with STM32F412GTx device. I’ve tried to configure the TIM1 as PWM,and enabled the interrupts in MX. Generated the code, opened in IDE, built and uploaded to the neucleo board with no significant problems. However, whilst the timer is configured pretty much as specified in MX, the timer is not enabled, none of the interrupts are enabled and the output is not enabled.I can see that whilst a motor control program would not want either the timer or the timer output enabled at boot, not having the interrupts enabled seems strange. I managed to enable these by looking up in the reference manual and manually setting the registers in the debug mode, but that does not affect the Flashed code. (Modifying CR1, DIER and CCER registers)I did find one article describing how to enable the timer, and added that code to the timer init function, but so far I’ve not found the commands

Environment:STM32CubeMX version: 6.18.1  STM32CubeIDE version: 2.2.0 STM32 MCU: SMT32H7R3Z8J6 OS: Windows 11Project configuration:Code Generator option: "Generate peripheral and middleware initialization as a pair of .c/.h files per peripheral (optional)" = [Enabled / Disabled] Relevant peripherals already enabled before: xSPI, USART1 New peripheral added that triggers the issue: USB_FS/HS, SPIx, UART/USARTx, and others. Description:When I add a new peripheral or middleware in STM32CubeMX and generate code, CubeMX creates an empty folder or generates incomplete peripheral and/or middleware output.The issue appears repeatedly with the same pattern and is not random. In the first case: Create or open project in CubeMX. In Project Manager / Code Generator, set: "Generate peripheral initialization as a pair of .c/.h files per peripheral" = Disabled (default).  Generate code.  Add a new peripheral: USB_FS (and/or others).  Generate code again. Open CubeIDE, then build. In the current situat

The linker file is expected to be in the root directory instead of the subdirectoryI have a project that has to compile for two STM32 hardware platforms:- the Nucleo-F446RE development board- the STM32G051 microcontrollerThe project is developed in VS Code.The .ioc file has been moved from the root directory to two subdirectories:./target/nucleo_f446re./target/g051In the file CMakePresets.json        {            "name": "nucleo_f446re",            "inherits": "default",            "cacheVariables": {                "CMAKE_BUILD_TYPE": "Debug",                "STM32_TARGET": "nucleo_f446re"            },            "toolchainFile": "${sourceDir}/targets/nucleo_f446re/cmake/gcc-arm-none-eabi.cmake"        }, The gcc-arm-none-eabi.cmake file is generated by STM32CubeMX. It contains the following line:set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32F446XX_FLASH.ld\"")This means that the linker script is expected to be in the root directory of the projec

Hi all,When I create a TouchGFX application starting from CubeMX, the following folder and its subfolders are not generated:{ProjectName}\Appli\Middlewares\ST\touchgfx_componentsGPU2D is enabled, and “Use GPU2D acceleration” is set to True under the X-CUBE-TOUCHGFX package settings.However, when I create a TouchGFX project using TouchGFX Designer and select the STM32N6570-DK, these folders are generated correctly.Am I missing a configuration step in CubeMX?Thanks so much!

The user authentication service is under maintenance on September 17 at 6:00 a.m. CET for approximately 30 minutes. During this period, disruptions can occur. The impact is limited to versions earlier than STM32CubeMX V6.16.0 and STM32CubeIDE V2.0.0. The service returns to normal soon after maintenance is complete.What to do if a problem occursIf issues occur during the maintenance window, use st.com or try again after 30 minutes. If the problem persists after that time, contact ST through the Community for further assistance. Update September 17, 2026:The maintenance was successfully completed as scheduled on September 17.If you encounter any issues, please do not hesitate to contact us.

Dear STM Community Team,We are working with the STM32N657X0H3Q microcontroller in our custom hardware design. We have interfaced S80KS5123GABHB020 Octal RAM devices with the controller using the XSPI interface.In our design, we are using a dual Octal memory configuration as described in the STM32N6 Reference Manual. The two 8-bit memories are configured to operate together as a 16-bit external memory interface.We would like your guidance regarding the correct STM32CubeMX configuration settings for this dual Octal memory setup.Our configuration details are: MCU: STM32N657X0H3Q External Memory: S80KS5123GABHB020 Interface: XSPI Memory Configuration: Dual Octal mode (two 8-bit memories forming a 16-bit interface) Intended usage: External RAM for (ltdc)framebuffer Memory mapped access: XSPI memory-mapped mode Could you please confirm the recommended STM32CubeMX settings for the following parameters? XSPI mode selection: Should the configuration be set as HEXASPI mode? Are

Hello everyone,I am experiencing an issue with STM32CubeMX version 6.18.0 right after a fresh installation. The software is unable to connect to the server to download repositories or updates.Here are the details of my situation:Network Environment: I am using my office Wi-Fi, which does not use a proxy server. Other applications connect to the internet without issues. Error Message: I keep getting a "Problem during server connection" error. Troubleshooting Done: I have already gone into the Connection Settings and tried changing the proxy settings to "No Proxy" as well as "System Proxy", but neither option resolved the issue. Since there is no proxy on our network, I am unsure what is blocking STM32CubeMX from reaching the server. Has anyone encountered this with version 6.18.0, or does anyone know which specific ports or URLs need to be whitelisted in our office firewall?Any help or guidance would be greatly appreciated. Thank you!

i have enabled FATFS via CubeMX like belowbut for some reason in the code generation settings I can’t disableI want disable it because CubeMX generates a void function; instead, I want the MX_FATFS_Init return a status code if it is generated or not so, I want to have a uint8_t MX_FATFS_Init() 

Looking at the Ethernet PHY circuit of the STM32H735G-DK, the MCU and MAC are connected via the RMII interface, and a pin named "RMII_RX_ER" is connected to the MCU.However, if you configure it for RMII in CubeMX (version 6.18.1), this pin does not activate normally. If the user manually activates it with the mouse, the pin is marked in yellow, meaning the function is not properly enabled Therefore, I checked the official Demo FW located in STM32Cube\Repository\STM32Cube_FW_H7_V1.13.0\Projects\STM32H735G-DK\Applications\LwIP\LwIP_TCP_Echo_Server\STM32CubeIDE, and even there, the pin is configured as GPIO_AF11_ETH. I am curious why it was designed and developed this way when it only gets configured but doesn't actually function. Is it just missing from the ETH group in the CubeMX DB? Or is it originally an unsupported feature, but ended up like this because an existing circuit design was just recycled?

I am really trying to report a problem/bug but I could not find straghtforward way to do it on the STM site. So here it goes:STM32CubexMx for certain object (like USBX) creates virtual folders with spaces in name. These cannot be resolved correctly by STM32CubeIDE (Eclipse) when they are reference links. Project Explore shows folders but with no files and they are not build.For example:UX Device CoreStackUX Device ClassesUX Host Stack The system the tool run under is Windows 11.

CubeMX Version 6.18.1 (tested with STM32G491VET6) shows no "Clear Input" parameter group for TIM16/TIM17, so the OCREF-clear feature cannot be configured from the tool.The hardware does support it, per RM0440 Rev 9:§31.4.17 "Clearing the tim_ocxref signal on an external event" (TIM15/16/17 chapter) TIMx_CCMR1 bit 7 OC1CE, x = 16..17 (p. 1490) TIMx_AF2 OCRSEL[2:0], x = 16..17 (p. 1505) selecting tim_ocref_clr0..7 Table 76 "Interconnect 3": TIM16/17 ocref_clr sources include the COMP1..COMP7 outputsUse case: cycle-by-cycle peak-current limiting of a synchronous buck (COMPx clears OC1REF; CH1N provides sync-FET freewheel). For comparison, TIM1/TIM2 panes do offer "Use ETR as Clearing Source" / "Clear Input Source".Currently the only workaround is manual register writes in USER CODE (TIMx->AF2 OCRSEL + TIMx->CCMR1 OC1CE), which the .ioc cannot capture.Request: add the Clear Input group (OC1CE + OCRSEL source selection) to the TIM16/TIM17 panes for STM32G4. Image 1: Outline of RM0440

  When enabling USB_OTG_FS peripheral in Device_Only mode for STM32H743VIT6, CubeMX generates usb_otg.c with incorrect HAL macros:Generated (wrong) Should be (H7-native) GPIO_AF10_OTG1_FS GPIO_AF10_OTG2_FS __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB2_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB2_OTG_FS_CLK_DISABLE  Root cause:  On STM32H7, the FS USB peripheral is USB2_OTG_FS, not USB1_OTG_FS. The H7 HAL defines GPIO_AF10_OTG2_FS for the FS port and GPIO_AF10_OTG1_HS for the HS port. CubeMX, however, generates F4/F7-style macro names (e.g. GPIO_AF10_OTG1_FS) which are only valid for MCUs with a single USB OTG peripheral.  Moreover, GPIO_AF10_OTG1_FS is conditionally defined in stm32h7xx_hal_gpio_ex.h only when USB2_OTG_FS is not defined. Since STM32H743 does define USB2_OTG_FS, the macro is absent at compile time.  The legacy compatibility aliases in stm32_hal_legacy.h could resolve this, but CubeMX does not include that header in the generated code.No

Dear ST Team,I am following the STM32 wiki guide:https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_STM32CubeMX_STiRoT_Boot_path_on_STM32H57While working through the steps, I encountered an issue with STM32CubeMX.The Boot Path and Debug Authentication configuration pages are blank and do not display the expected options shown in the tutorial. Because of this, I am unable to continue.STM32CubeMX Version: 6.18.1 Could you please advise how to resolve this issue?Thank you for your support.Best regardsRJ

I am trying to configure the clock for the STM32L496 microcontroller, as shown in the screenshot below.I would like to use MSI in PLL mode with the LSE. When I configure the LSE in CubeMX, the 'MSI Auto Calibration' option disappears. When the LSE is disabled, the option is visible, but it cannot be enabled.Please tell me how to correctly configure MSI in PLL mode with the LSE in CubeMX.

Hi everyone,I am working on a dual-core project using the STM32H757Xi and running into an issue with STM32CubeMX regarding NVIC interrupt assignment for the Cortex-M4 core.Here is my setup and the problem I am facing: Microcontroller: STM32H757Xi Toolchain: STM32CubeIDE v1.19 Goal: Configure two Memory-to-Memory (M2M) DMA channels assigned to and running on the Cortex-M4 core. Issue details: In CubeMX (under System Core -> DMA), I created two M2M channels: DMA2 Stream 6 and DMA2 Stream 7. I also tested the exact same configuration using DMA1 Stream 6 and DMA1 Stream 7. In both cases, when I check the NVIC settings, the Interrupt Request (IRQ) checkboxes and priority settings for these streams are only active under NVIC1 (Cortex-M7). Under NVIC2 (Cortex-M4), the corresponding IRQ checkboxes are completely greyed out and disabled. Because CubeMX thinks these interrupts belong to NVIC1, it generates the DMA interrupt handlers in stm32h7xx_it.c for the M7 core context instead of

Hi,When attempting to install a package "From local" on a development PC that is offline, CubeMX rejects the package with the error message "package not recognized."How can the package dictionary (XML file) be updated? This would be the offline equivalent of the "Refresh" button. Thanks

Summary STM32CubeMX (STM32U5 targets; reproduced with 6.18.0-RC3 and 6.18.1-RC2) generates an incorrect clock-disable call in the LSE bring-up block of HAL_RTC_MspInit() in Core/Src/rtc.c. The restore path that is meant to switch the PWR peripheral clock back off passes an AHB3 peripheral mask to the APB1 disable function:/* Restore clock configuration if changed */if (pwrclkchanged == SET){LL_APB1_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PWR); /* generated — wrong bus group */}The matching enable earlier in the same function is generated correctly:if (LL_AHB3_GRP1_IsEnabledClock (LL_AHB3_GRP1_PERIPH_PWR) != 1U){/* Enables the PWR Clock and Enables access to the backup domain */LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);pwrclkchanged = SET;} DiagnosisOn the STM32U5, the PWR peripheral clock lives on AHB3, and the two enable registers happen to use the same bit position:Register Bit 2 Reference RCC_AHB3ENR PWREN — PWR clock enable RM0456 Rev 5, §11.8.32, p. 558 RCC_APB1ENR

Kindly suggest the root cause 

Hello everyone, I have seen that is possible to generate a pdf report using STM32CubeMX (version 6.18.1) as shown in the image: Is there a way in order to launch a command line to run this operation? In order to automatize my development process.Thank you in advance, Alberto

Using STM32CubeIDE v1.17 (STM32CubeMX v6.13) to edit IOC file and generate code...Previously when working with STM32H563 I selected X-CUBE-FREERTOS under Middleware, added tasks, generated code, and saw expected code in app_freertos.c for tasks.Now starting to work with STM32G491. Under Middleware I see FREERTOS but no X-CUBE-FREERTOS. After adding a task and generating code, I see nothing in app_freertos.c for the task. What is the difference between FREERTOS and X-CUBE-FREERTOS?Why don’t I see X-CUBE-FREERTOS when working with STM32G491? 

Hello, I was trying to solve the issue of this ticket: But, as you can see on the image that I am sharing, I cannot change the FreeRTOS type zone. How can make my project work?