Edge AI

Hello the community !  I would like make sound detection default with the B-U585I-IOT02A I had use the nanoEdgeAI studio, create my project, with microphone (picture 1) I had create the data logger Analog 1 axis (picture 2) And i have this curves, is this normal ? with or without sound i have the same curves. (picture 3) thanks.  

I have implemented streaming speech recognition on the STM32N6, with a model designed specifically for the constraints of this microcontroller and its NPU.The STM32N6570-DK listens to its on-board microphone and prints the text on the display. It recognizes any English words, not a fixed list of commands, and works with no network connection. The word error rate on LibriSpeech test-other is 14.84% with no language model.Source code, model weights and ready-to-flash firmware: https://github.com/fotonik-sk/stm32n6-asr

Hello,I’have managed to define/train/quantize/translate_for_target a model so far. The target is the STM32N6.I have also managed to run the model on the target by an own script using airunner functions/methods.The last step remaining is to get rid of the airunner-magic so that i can integrate the created .c/.h (by stedgeai) into my own framework on the target. Observation 1:I first noticed that the memory location of the weights is neither az 0x7100_0000 nor at 0x7038_0000 as suggested by the output.From network_generate_report.txt:octoFlash  [0x70380000 - 0x71380000]:     60.095 kB /     16.000 MB  (  0.37 % used) -- weights:     60.095 kBFrom the generated C-File network_atonbuf.xSPI2.c (as a comment):/* index=8 file postfix=xSPI2 name=octoFlash offset=0x71000000 …. */LL_ATON_ALIGNED(64) const uint64_t _mem_pool_xSPI2_network[7693] = {It finally ended up at 0x701253c0. I have a hard time underrstanding which tool is relocating the buffers from where it is initially supposed to live.

Setup- Board: STM32N6570-DK, Neural-ART NPU, dev boot.- Tool: ST Edge AI Core 4.0.1 (target stm32n6), ll_aton 1.1.3.275 / NetworkRuntime1201_CM55_GCC.a.- Model: ViT-style autoencoder encoder. Input 1×3×256×256 RGB, output INT8 [128,12] → 128 LE-uint16 tokens (256 B). Weights in xSPI2 NOR @ 0x70380000.Problem 1 — wrong latent (NPU)The board latent doesn't match ONNX Runtime on the compiled graph (0/128 tokens). Epoch tracing shows input, weights and the first conv are correct, but the first Concat output is placed by the planner on top of one of its inputs:input1  [1,256,512] @0x34310000output  [1,257,512] @0x34310000   (starts where input1 starts)LL_ATON_LIB_Concat copies inputs in order with forward memcpy, so it corrupts the tensor (every row becomes the class token). I added an overlap-safe copy as a local patch; that fixes the Concat, but a second fault remains in epochs 8..72 (first LayerNorm / start of the first attention block) → latent still wrong.Problem 2 — speedOne encode is

When training a standard model (e.g. `mobilenetv2_a035`, `pretrained: True`) for image classification on a custom dataset with 2 classes, training crashes at the first epoch:ValueError: Arguments `target` and `output` must have the same rank (ndim).Received: target.shape=(None,), output.shape=(None, 2)I’m working with: Windows, Python 3.12, TensorFlow/Keras 3My minimal user_config.yaml to reproduce the error:model:  model_name: mobilenetv2_a035  input_shape: (224, 224, 3)  pretrained: Truedataset:  class_names: [class_a, class_b]training:  dropout: 0.3 My analysis is the following:1. `get_mobilenetv2()` (`image_classification/tf/src/models/mobilenetv2.py`) correctly builds a binary head when`num_classes == 2`: `Dense(1, activation="sigmoid")`.2. `api.get_model()` saves the freshly built model and sets `cfg.model.model_path`.3. Because `model_path` is now set, `ICTrainer.prepare()` (`tf/src/training/ic_trainer.py`) calls `change_model_number_of_classes(self.model, self.num_classes)`.4.

Hi ST Support Team,We encountered a reproducible HardFault when running an object detection model on the STM32N6570-DK, and have completed extensive isolation testing. We believe this points to an issue in the STEdgeAI 4.0.1 / Neural-ART toolchain combined with the Getting Started reference application (concurrent camera/display/NPU usage), rather than a configuration mistake on our side.[Environment]- Board: STM32N6570-DK (with IMX335 camera)- Project: Getting Started Object Detection App (stm32ai-modelzoo-services)- Model: st_yoloxn (1 class, 416x416), Quantized (input: uint8 / output: int8)- Toolchain: STEdgeAI Developer Cloud v4.0.1 (forced by cloud; v4.0.0 is no longer offered, though the project's own README states the shipped model files were generated with v4.0.0)[Symptom]Build, flash, and boot-from-flash all complete without error, but the LCD stays black. Debugging via STM32CubeIDE shows a HardFault during NPU inference:HardFault_Handler()__LL_ATON_RT_IrqErr(irqs)   // ll_ato

Hello,I’m working with a NUCLEO-N657X0-Q board and trying to run inference using the ST Edge AI embedded client API. The STM32CubeIDE project I’m using was generated with CubeAI Studio. Input, output, weights and activations buffers are preallocated. Here are the advanced settings I used in CubeAI Studio: Even though the validation with CubeAI Studio was successful, I edited the app_x-cube-ai.c file in order to validate my samples again so that I know I’m feeding data into the network and obtaining the outputs correctly. This is were I noticed that the prediction of every single sample is incorrect. Since I got over 98% accuracy with CubeAI Studio, I assume I’m doing something wrong in my code. Unfortunately, I can’t really figure out what it is. I only made a few minor changes to the app_x-cube-ai.c template. I’m basically interacting with the network like follows:static float* input_states_ptr;static float* input_currents_ptr;static float* output_states_ptr;static stai_ptr stai_input

Hello,Recently I decided to run STM32N6 NPU under non-secure Zephyr and encountered a bug in LL_ATON library. To begin with, this is my platform and SW:Board: NUCLEO-N657X0-QSoC: STM32N657X0H3QLL_ATON: atonn-v1.1.3-275-g6770925dRuntime: NetworkRuntime1201_CM55_GCC.aSTEdge AI: v4.0.1-20581 7ed50de05   ISPU 2.0.1-RC2   MLC 1.2.4-RC2   STM32CubeAI 12.0.1-RC2Model: st_yolodv2milli_actrelu_pt_coco_person_192_qdq_int8.onnxSW: OEMUxROT (S) + Zephyr (NS)XIP: enabledMy application runs in non-secure world and the NPU keeps addressing AXISRAM3-6 through the secure alias (0x342...), so the memory pools in the generated network are placed there. Then, the non-secure CPU is unable to access that alias, because it is running in non-secure and should access via non-secure alias (0x242...). In most cases LL_ATON utilizes ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR to access correct region, but there are few places that pass address directly instead of utilizing proper macro.Reproduction steps:1. Run a network f

Tool: ST Edge AI Core v4.0.1-20581 (7ed50de05), target stm32n6Neural-ART compiler: 1.1.3-275Runtime: ST Neural ART (LL_ATON api) v1.1.3, atonn-v1.1.3-275-g6770925dBoard: STM32N6570-DK, device 0x486, Cortex-M55Host: Windows 11, STM32CubeProgrammer 2.23.0, gnu-tools-for-stm32 14.3.1WHAT HAPPENSA 23x60 -> 30x5 INT8 TCN, generated for stm32n6 with the Neural-ART compilerand run on the NPU, returns an output that is not the INT8 graph's.This is not an application bug. "stedgeai validate --mode target", run againstyour own NPU_Validation project with your own random stimulus, reports theboard's output as essentially uncorrelated with the reference model thenetwork was generated from:  acc=n.a. rmse=2.543027878 mae=1.976331592 l2r=1.100639820  mean=-0.346161 std=2.520198 snr=-5.872663 nse=-2.889206 cos=0.091053cos 0.091 is no correlation. snr -5.87 dB is noise above signal. nse -2.889 isworse than answering with the mean of the reference. l2r 1.10 is an errorlarger than the quantity it is

As i was going through the tutorialhttps://dev.st.com/edge-ai-docs/general/latest/en/docs/tutorials/how-to-deploy-ai-model-stm32n6-neural-art.htmli have faced issues in the linker script.The tutorial’s linker-script example places model data in EXTFLASH using the *_atonbuf.xSPI2*(.rodata*) pattern. In my generated project, however, the model weights are emitted in Application/User/AI/network.o as .rodata._ec_blob_network_* sections. Those sections didn’t match the example’s pattern, so the general .rodata* rule placed them in ROM instead.This caused .rodata to extend past the ROM boundary at 0x70180000 and overlap .AI_XSPI2. Adding *(.rodata._ec_blob_network*) to the .AI_XSPI2 section moved the model blobs into EXTFLASH and fixed the link.Please consider updating the tutorial to mention that generated model-section names can differ, and show how to check the linker map and route the generated model blob sections to EXTFLASH.the solution for me was to update the linker script with this.

As shown on the website below, the Arc Fault Circuit Interrupter (AFCI) solution is introduced as an Edge AI use case.https://www.st.com/content/st_com/en/st-edge-ai-suite/case-studies/direct-current-arc-faults-detection.htmlFor hardware development reference, would it be possible to purchase the development board shown on the page?It would also be helpful if you could share the schematic and BOM of the PCB.

Hello, I just started in stm32 system, I want to ask for stm32N6 series can use other camera module? such as camera product from Arducam where the product is made for raspberrypi systemwhich uses CSI-2 interface, here product link : https://www.arducam.com/product/64mp-quad-camera-kit/Thankyou

Hello,The Neural-ART compiler (atonn) crashes with an internal assertion when I run `analyze` on a quantized 1D CNN. The crash happens on the pooling unit and I cannot get past it.EnvironmentST Edge AI Core v2.2.0-20266 (X-CUBE-AI 10.2.0), Windows, via STM32CubeMX Target: stm32n6 Also reproduced on ST Edge AI Developer Cloud with ST Edge AI Core v4.0.1-20581 -> same assertion, so this does not look version-specific.Model Keras model exported to TFLite, full int8 quantization (int8 input and output, per-channel), batch size fixed to 1.Architecture (1D CNN for signal classification):  Input [1, 3000, 1]  3x { Conv1D -> BatchNormalization -> ReLU -> Dropout -> MaxPooling1D(pool=2, stride=2) }     conv filters = 128 (k=30), 32 (k=20), 4 (k=10), padding 'same'  Flatten -> Dense(512) -> BN -> Dense(128) -> Dense(32) -> Dense(4, softmax)Input tensor quantization has a non-zero zero-point (scale ~0.0366, zp -2).When converted, TFLite lowers the model to CONV_2D (x

Hello ST team, I am trying to run an ONNX model on a NUCLEO-U545RE-Q board using STM32Cube AI Studio I first tried with a model of about 281.75 KiB weights, and the generated project failed at build/link stage with an undefined UART symbol. To check whether the issue was related to memory size, I also tried a smaller model: - Model: model_seqlen20.onnx- Input: f32(1x20x25)- Output: f32(1x1)- Parameters: 32,129- Weights: 128,516 B / 125.50 KiB- Activations: 2,256 B / 2.20 KiB- Total AI flash reported: 130,190 B- Target: stm32u5- Board: NUCLEO-U545RE-Q- Firmware package: STM32Cube_FW_U5_V1.9.0- ST Edge AI Core: v4.0.1-20581- Toolchain: STM32CubeIDE The model generation step completes successfully. The reported memory footprint is small enough for the board. However, during the Run flow, STM32Cube AI Studio the build fails with: undefined reference to `UartHandle` The errors are: Middlewares/ST/AI/Misc/Src/aiTestUtility.c:- _put_c_driver: undefined reference to `UartHandle`- ioRawWriteBuf

Hello,I've got a problem with displaying an image classification AI on my board. So far I've been following this tutorial:https://wiki.st.com/stm32mcu/wiki/AI:How_to_use_Teachable_Machine_to_create_an_image_classification_application_on_STM32starting from step 3, as I already have a trained AI model as .tflite file.The execution with the .yaml file is working fine, it's flashing but the display is only showing artifacts.Hardware details:STM32H747I-DISCO: MB1248-H747I-D03- LCD Daughterboard: MB1166-A09- Panel Controller: NT35510B-CAMS-OMV:Camera module adapter board: MB1683-CAMS-A02- Camera module:  MB1379-2V8-A05- Image sensor: OV5640The display was a newer version so I changed the defines inapplication_code/image_classification/STM32H7/Application/STM32H747I-DISCO/Inc/CM7/stm32h747i_discovery_conf.hto this:#define USE_LCD_CTRL_OTM8009A             0U#define USE_LCD_CTRL_NT35510                1U#define USE_LCD_CTRL_ADV7533                0UThe nt35510.c and .h files already existed in

Board: NUCLEO-N657X0-Q (MB1940), STM32N657X0H (Cortex-M55 + Neural-ART NPU), Device ID 0x486 Rev Z.Toolchain: ST Edge AI Core v4.0.1-20581 (STM32Cube.AI 12.0.1-RC2), atonn 1.1.3-275, NetworkRuntime1201_CM55_GCC, arm-none-eabi-gcc 14.3.1 (STM32CubeCLT 1.21.0). SUMMARYA small int8 QDQ model (TCN: Conv2D x7 + Gemm x2, macc ~2.37M, int8 weights ~20 KB) generated with "stedgeai generate --target stm32n6 --st-neural-art" runs to completion on the NPU but produces wrong outputs: high-input forecasts collapse to baseline. Independent cross-check: onnxruntime on the same int8 ONNX gives 9.664 (ppm, log-domain output dequantized) on our golden window; the NPU returns ~0.26. Confirmed on hardware with ST's own "stedgeai validate --mode target" (regression head rmse 8.78, cos 0.589 vs the reference). LOCALIZED ON-TARGET TO A SINGLE OPPer-layer on-target validation (backbone stage outputs exposed as ONNX outputs):- input projection Conv: cos 0.999 (correct)- block 0 (dilated Conv + Slice + residual

Hi all, Any well defined step by step for STM32N6 disco board? a link would be appreciated.  Thank you. 

Hello, I recently encountered this error while deploying an AI model on an STM32N647 for performance verification. I noticed that others have encountered the same issue on the official website, but following the suggested solutions did not resolve my problem—I’m still getting the same error. This issue has been troubling me for a week now. Are there any other ways to resolve it? 

I'm currently developing with the STM32N6570-DK, using STM32N6 1.4.0 firmware, and using AI Studio and CubeMX to generate projects.However, I've encountered a very confusing problem. In the program generated by AI Studio, after calling MX_EXTMEM_MANAGER_Init() in the FSBL, it calls functions like BSP_XSPI_NOR_Init() and BSP_XSPI_RAM_Init(). This seems to be an additional Flash and SRAM driver written separately by the official documentation. /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_XSPI1_Init(); MX_XSPI2_Init(); MX_EXTMEM_MANAGER_Init(); /* USER CODE BEGIN 2 */__HAL_RCC_AXISRAM2_MEM_CLK_ENABLE(); __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE(); __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE(); __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE(); __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();/** Workaround for an issue generated in STM32CubeN6 FW 1.4.0 **/ extern XSPI_NOR_Ctx_t XSPI_Nor_Ctx[XSPI_NOR_INSTANCES_NUMBER];

Hello ST Community,I am working with the STM32N6570-DK and running a custom-trained ST YOLOX Nano object detection model using the STM32N6 Getting Started Object Detection application.My custom model has 5 classes.The model is successfully generated and integrated into the STM32N6570-DK object detection project. The application starts correctly, the camera/display starts running, and I can see a few frames initially.However, after processing a few frames, the display freezes/stops updating. The board itself does not appear to continue normal inference after this point.I also noticed an unexpected LED indication on the board. This LED was not active when I previously ran the standard/reference object detection model. I have attached photos of the front and back of the STM32N6570-DK showing the LED state. My setup is:Board: STM32N6570-DK Application: STM32N6 Getting Started Object Detection Model: Custom ST YOLOX Nano Input: 480 x 480 x 3 Number of classes: 5 Camera: ST camera module con

Hello ST Community,We are currently using the x-cube-n6-ai-face-landmarks pipeline on the STM32N6570-DK. We now want to extend the BlazeFace stage so that it can detect additional DMS-related classes along with face detection. The classes we are interested in are:Phone, Seatbelt, Smoking, Face, Drinking. At present, the BlazeFace model used in the ST face-landmark project is a single-class face detector, and we could not find a public ST training pipeline for retraining or extending this specific BlazeFace model. Is there any ST example or reference repository for training BlazeFace on:WIDER FACE, custom datasets, or custom multi-class datasets?Our goal is ideally to reduce the number of separate detection models while keeping the existing face-landmark pipeline functional on STM32N6570-DK.Any guidance on the recommended training flow, supported model architecture, or available reference code would be very helpful.

Built a minimal on-device training stack for STM32 — fits in 608 bytes RAM total.The problem: Adam optimizer needs exp_avg + exp_avg_sq — 2× parameter RAM. On STM32F103 (20KB SRAM) with a 5K parameter model that's 40KB just for optimizer state. Doesn't fit.What I built:GravOptMini — momentum optimizer with quantile-based gradient freeze. Only exp_avg (1× param RAM). Freezes low-gradient parameters to reduce compute.W-Twin Lite — power-law baseline fitted on early steps, tracks deviation. Pure float32, no scipy, no numpy. Rolling window of 20 values. ~240 bytes.Benchmark (Python simulation, STM32 memory constraints):- Model: 46 params, 184 bytes- GravOptMini state: 368 bytes (exp_avg only)- W-Twin Lite: 240 bytes- Total: 608 bytes- MNIST accuracy: 93.2% vs Adam 97.4%- W-Twin overhead: 3.9% per step- Detection: anomaly caught 96 steps before visible loss divergence, 0 false alarms on clean runNext step is a real STM32 test with physical hardware. C port of both components is the plan.Has

Hi everyone,I’m working with the STM32N6570-DK (STM32N6 Discovery Kit) and noticed that the example projects/scripts configure the external flash memory as 16 MB in the linker script.However, as far as I understand, the Discovery Kit supports 32 MB of external flash.I’m trying to understand why the linker scripts are configured for only 16 MB.For example, if the linker script contains something similar to:FLASH (rx) : ORIGIN = ..., LENGTH = 16MI have a few questions: Why is the linker script configured for 16 MB when the board supports 32 MB? Is the 16 MB value simply a default/example-project configuration, or is there a technical reason for it? Can the FLASH region safely be changed from 16 MB to 32 MB? Are there any restrictions related to the STM32N6 memory map, OCTOSPI/XSPI configuration, boot process, linker script, MPU/cache configuration, or startup code? If I want to use the complete 32 MB, are there any other project files or configurations that need to be modified in

Stm32cubeAI studio output      -------------------------------------------------------------------                       STM32CubeProgrammer v2.23.0                        -------------------------------------------------------------------ST-LINK SN  : 0042001A3234510337333934ST-LINK FW  : V3J17M10Board       : NUCLEO-N657X0-QVoltage     : 3.30VSWD freq    : 8000 KHzConnect mode: Under ResetReset mode  : Hardware resetDevice ID   : 0x486Revision ID : Rev ZDevice name : STM32N6xxDevice type : MCUDevice CPU  : Cortex-M55BL Version  : --Opening and parsing file: NUCLEO-N657X0-Q_Appli.elfMemory Programming ...  File          : NUCLEO-N657X0-Q_Appli.elf  Size          : 2.60 MB   Address       : 0x34000000Erasing memory corresponding to segment 0:Erasing memory corresponding to segment 1:Erasing external memory sectors [16 57]Error: failed to erase memoryError: failed to erase memoryRun failed: Error: STM32CubeProgrammer exited with code 1 

LL_ATON_LIB_Concat falls back to 4× memcpy when the concat axis is not leftmost — 32% of a 4 ms real-time budget on STM32N6Hardware: NUCLEO-N657X0-Q (STM32N657X0H3Q), Cortex-M55 @ 800 MHz, Neural-ART. Tools: ST Edge AI Core 4.0, STM32Cube_FW_N6 V1.4.0, STM32CubeIDE 2.1.1. Application: real-time audio, hop = 192 samples @ 48 kHz = 4 ms = 3.2 M cycles, hard deadline, underrun must stay 0.1. Concat falls back to a byte loop, and it is one third of the budgetOur graph is a streaming TCN (int8, L=12, C=88, T=48) run per audio hop with two voices, so the tensor layout has the voice axis leftmost: [C][V][T]. The graph contains 12 Concat blocks (channel-wise taps).Epoch profiling (LL_ATON_EB_DBG_INFO, DWT cycle counter on the M55) showed those 12 blocks costing 1 019 501 cycles per inference — 32% of our entire 4 ms budget. No compiler option changed the number.The cause is in the runtime source: LL_ATON_LIB_Concat takes its fast DMA path only when the concatenation axis is the leftmost signif