Others: hardware and software

Hi there,We are aiming to use the E-TDA7391PDTR in our new design and we would like someone from ST to share the relationship between C3, R2 and the Mute/sync pins, as the older related question does not explain much and does not resolve the issue in case we want to change the values. The datasheet does not have any explanatory section on the working principles of the chip, so no relevant info is found there.For reference: Many thanks in advance.Best regards,Manuel Gomez Galan

Hi everyone,I’m looking for the BGA pinout of an ST device marked H418-HUB, which I believe is an STiH418.I found the public data brief (DocID026633) and the Linux device-tree sources, but I’m missing the mapping from the logical PIO signals to the physical BGA balls. Specifically, I’m trying to locate: UART10: PIO3[4] (TX) and PIO3[5] (RX) SPI-FSM: PIO40[0–5] Does anyone know where to find the package ball assignments and the corresponding I/O voltage specifications? I would also be interested in the full hardware reference manual, particularly the sections covering pin multiplexing, UART and SPI-FSM. If access to the complete manual is restricted, a pinout table or an extract covering these interfaces would already be helpful.I also found references to the 4kopen B2264 board, which used the same SoC and offered schematics and an ST MicroConnect 2 JTAG connection document. However, the 4kopen project appears to have been abandoned: its former website and documentation resources are

Hello, we plan to power the STPM32 only briefly at each measurement (every ~2 s),so we need its settling time after power-up/reset, which is not in thedatasheet (DS10272 Rev 14). On the EVALSTPM32 (12 V AC 50 Hz on L/N, default configuration after aglobal reset) we measured:- V1 RMS within 1% after ~400 ms, with or without the DC-removal HPF;- with the HPF enabled, a DC of ~2 V (at the input) in V1 Data that decays to < 0.1 V only after ~1.7 s, although the datasheet states -3 dB at 8 Hz;- the same DC shifts the ZCR edges (rising and falling in opposite directions) until it has decayed. Questions:1. After power-up (EN) or a global reset, how long should we wait before the  RMS values and the ZCR output are accurate? Is there a typical or  guaranteed value?2. The DC-removal filter is specified at -3 dB at 8 Hz, but at start-up it  takes ~1.7 s to remove a ~2 V offset. Why is it so slow? Does the offset  come from the analog front end settling after reset? Is there a setting  to make

Hello, The STM706 is setup with the WDI pin pulled low via 10K resistor, all other pins are in a normal state (VCC high). When the WDI pin is probed in this condition a 200ms, 500mV pulse can be seen every 1.7 seconds. Is this the pulse referenced in the datasheet section 3.3 and is it expected performance?Thanks,Diarmuid

Hi,I’m debugging intermittent DID_VID read errors on an STPM4_RASPI v1.2 evaluation board with an ST33TPHF2XSPI. The host is an Arty A7-100T FPGA. The interface is SPI mode 0 at 10 MHz with 3.3 V I/O, and the TPM board is powered from the Arty’s PMOD 3.3 V supply.When I repeatedly read four bytes from DID_VID using the SPI header 83 D4 0F 00, the TPM returns the expected value, 4A 10 00 00, for an extended period. Incorrect responses occur intermittently after many successful reads. On a failing read, I observed 81 FF 81 FF when locality 0 was inactive and A1 FF A1 FF when it was active. Acquiring and releasing locality without resetting the TPM changed the incorrect response accordingly.In the Saleae captures, the DID_VID header on MOSI is correct, the incorrect bytes are visible on MISO, and CS stays low through the header, wait, and data phases. Incorrect reads typically show about 15 wait bytes in our logs, versus about one for correct reads. The issue occurs at both 1 ms and 1 s p

Hi,Could you please provide:T_Jmax (maximum Junction Temperature) R_JA(Junction to Ambient Thermal Resistance) R_JC (Junction to Case) R_JB (Junction to Board)for the M24128-DRMF3TG/K.

We have the parts ST712FR2T6  and we have tested them according to datasheet. Passed all visual, electrical, solderability and X-ray. What we’re concermed about is the date code and Bulk ID.1. Can you confirm that ST used this marking ST712FR2T6?2. Confirm that the Bulk ID is the ID of ST Micro?3. Confirm if the DC is 2023 or 2013? We’re aware the EOL of parts was 2021 

can i get help identifying this part  

Good evening Where can I find the body marking  information for the M95512-DFMC6TGM component?Thank you.Best regards.

Hello everyone,I am working on a custom locker controller board based on the STM8S208CBT6 in the LQFP48 package. I am using the Cosmic C Compiler inside the STVD environment and flashing the MCU via STVP with a standard ST-Link V2 clone.I am experiencing an issue where two specific pins, PD0 (Pin 41) and PC7 (Pin 34), are stuck at a constant logic high level ('1') when configured as standard digital inputs with internal pull-ups (GPIO_MODE_IN_PU_NO_IT), completely ignoring external buttons / shorts to GND. At the same time, six other GPIO pins configured exactly the same way work perfectly fine and detect shorts to GND without any issues.Here is the hardware configuration and what I have observed so far:1. PD0 (Pin 41) is multiplexed with TIM3_CH2, TIM1_BKIN, and CLK_CCO. On this 48-pin package, it is also right next to the SWIM pin (Pin 40). 2. PC7 (Pin 34) is multiplexed with SPI_MISO.3. The board relies on standard UART1 (TX on PA5, RX on PA4) for RS-485 communication, which must re

where can post techinical request about GAN device question

 Dear STMicroelectronics Technical Support Team,We are experiencing a target detection and firmware programming issue with an ST-LINK debugger manufactured in Vietnam and purchased from DigiKey.We are using the STM32H750VBT6 microcontroller on our custom development board and programming it through STM32CubeIDE and STM32CubeProgrammer.We have tested two ST-LINK debuggers on the same development board. One debugger, manufactured in China, works correctly, while the other, manufactured in Vietnam, fails to detect the target microcontroller.1. Working ST-LINK Debugger (Made in China)When the debugger is powered without connecting it to the target board: 3.3 V pin voltage: 3.3 V SWDIO pin voltage: 3.1 V After connecting it to our STM32H750VBT6 development board: Development board supply voltage: 3.3 V ST-LINK 3.3 V pin voltage: 3.3 V SWDIO pin voltage: 3.18 V STM32CubeProgrammer detects the ST-LINK successfully. Target voltage reported: 3.13 V Target MCU is detected successfull

Dear STMicroelectronics Support Team,We are currently investigating a potential EEPROM data integrity issue involving the M95320-A125/A145, and we would appreciate your urgent technical guidance.Our product is already deployed in the field, making this issue particularly critical.1. Application and Write ScenarioOur application uses the M95320 EEPROM, and we repeatedly write data to address 0x1CF.The relevant ECC group is 0x1CC–0x1CF, as described in the Error Correction Code (ECC × 4) section of the datasheet.Our SPI trace confirms that the application sends a single data byte when writing to address 0x1CF. We do not explicitly write to the other three addresses in this ECC group.The relevant SPI transaction is:MOSI: 02 01 CF F8Where: 0x02: WRITE instruction 0x01CF: Starting address 0xF8: Single data byte According to the datasheet, although a single byte can be written independently, the other three bytes in the same ECC group are also affected in terms of write cycling.2. Applic

Hello,can you identify this component? ST   W7X428CHINABUL 380A Thank you!regardssonic21 

I'm currently working on an amplifier stage for a COHO Driver. I'm posting with a general question on the characterization for this transistor. The PD55003-E came up as a candidate for my coherent oscillator amplifier stage. Since the FET's datasheet specifies higher frequencies I was wondering if there were any tests done rated around 55-59 MHz with a Class A amplifier. The design includes a 17 dBm input and a 27 dBm output. The general worry is that with the lower frequency requirement that these dBm specs won't work in the testing stage. This is only the second amplifier I have designed so bare with me if I missed any crucial information on the datasheet.

Are the 4 MSbits of the M24M04E-F slave address completely fixed at 1010? So incompatible with another I2C peripheral on the same bus sharing the same 4 MSbits slave address, yes? Is there a clever way around this? (I know it can be changed on the M24M02E-F.)

I’m making AOI program for STSAFA110DFSPL02 and would like the correct top marking because I couldn’t find it in the datasheet.The received part has SF3C B317 marked in the top side and need to confirm that is correct or not.

For TS972IQT, how to determine whether the DC  is 2013+ or 2023+ ?  thanks~

Hello am designing a 6S battery pack (25 V nominal) around the BQ40Z80 and would appreciate your feedback on my schematic before I proceed to layout. I used the BQ40Z80 EVM reference design (datasheet Figure 7-1) as a starting point and adapted it for a higher current.Design summary -Cells: 6S (VC1–VC6), with 100 Ω / 100 nF RC filters on each cell input.- Current: 60 A continuous, 80 A peak (the charge current is lower).- Current sense: 1 mΩ shunt on SRP/SRN, which gives about 75 mV at 75 A. This is within the ±100 mV input range of the device.- Protection FETs: 3× BSC014N06NS in parallel on the CHG side and 3× in parallel on the DSG side, in a common-drain back-to-back configuration.- Gate drive: single gate resistors per FET (1 kΩ on the CHG side, 12 kΩ on the DSG side), 10 MΩ gate-source resistors, and clamps on the gate-source of the DSG FETs.- Pre-charge/pre-discharge: P-channel MOSFET (Q41) in series with a 100 Ω / 3 W resistor (R140), driven by a BSS138 from LEDCNTLA (PCHG is no

Hi,Can we use a ferrite bead with STM8S MCU for VCC pin along with the recommended decoupling capacitors at the VCC pin. Thanks in advance.

Hello ST team,I am designing a custom three-phase inverter using the STDRIVE102BP to drive a 24 V, 26 W BLDC motor. I would like to clarify the recommended external connections for VS, VCC, REGIN_3V3, and VDD.I have reviewed the datasheet and the EVLDRIVE102BP schematic, but I am still confused about the power supply configuration. Are separate external 12 V and 3.3 V supplies required? Do I need to supply VS with an external 12 V source and REGIN_3V3 with an external 3.3 V source?Alternatively, if I use an external 3.3 V supply, should REGIN_3V3 and VDD be connected together to bypass the internal 3.3 V LDO? Does this bypass require any SPI configuration, or is it implemented entirely through the external connections? How is the evaluation board powered in its default configuration? In the EVLDRIVE102BP schematic, REGIN_3V3 is connected to VCC through JP4, with pins 1–2 shorted by default.VS appears to receive power from the external supply through the board’s connections. Initially,

hi good day,may we seek your expertise regarding discrepancy on assembly origin in packaging vs country origin on top marking of the chip.is it correct to interpret that China is the country of diffusion(wafer) and Italy is the final assembly and testing?thank you very much for enlightenment.

In our Project CAN communication isestablished via CANtrcv TJA1145, the INH is triggering the wakeup to L99ASC03, then the watchdog present in L99 is triggering to switchof MCU so I need to control the Watchdog via SPI by writing the value to its register as in L99ASC03 Datasheet shown below, could you please support how shall I implement this to send via SPI.​​​​​ 

Hi, As mentioned in the other post that the drone frame is not symmetrical, where the propeller guards have fins with certain inclination and orientation (see [1]). I have difficultly to find the correct orientation of the drone02 frame. Since I am not quite sure how the propeller guards fins can affect the downward thrust that produces by the propellers. It would be great if someone can provide suggestion.  I enclosed two cases of the drone frame orientations as reference. NOTE: If I use Figure8 in [2] as reference, then Case1 does look correct. But taking the M2 propeller (top right of the propeller) as an example, the M2 propeller rotates counter-clockwise (CCW) direction, then I think the produced thrust will hit the guard fins and get affected?  Case 1  Case 2  Case 1: top right (for M2 motor/propeller)  Case 2: top right (for M2 motor/propeller)   Ref:[1] Steval-FCU001V2 FCU board and Steval-drone02 Drone kit issues[2] ST, How to build your own mini d

Described below method is intended to perform correction of the static ADC’s non-linearity in software using LUT. It requires pure sine-wave source only, that can be generated by any available analog circuitry. Basically, it corrects non linearity induced by signal conversion analog front end all together, that includes ADC and it’s drivers, signal conditioning / amplification stages, inputs protection, etc. There is a way to do the same linearity correction by applying linear ramp voltage and generating error LUT table. New method is using sine-wave, and consequently has a few advantages over “classic” : 1. Linearity of the sine-wave is much more easier to verify down to -140 -160dB (0.1 – 0.01 ppm) using simple tween-T notch filter. 2. Analog front end may include DC blocking capacitors. 3. Calibration test signal could function in the “working band” area, and some complex dynamic distortion of the drivers (due to fall of the AOL over frequency, output stage