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When I was using STM32N6, I tried to generate USART with STM32CubeMx, but when you enable DCache the DMA did not properly handle USART-RX data.The USART startup code is as follows static FIXED_DMA_USER_RAM uint8_t s_ulDebugUsartRxDmaFifo[16]; bool DevUsartInit(void) { bool ret = false; //HAL_UART_DeInit(&huart1); //MX_USART1_UART_Init(); memset(s_ulDebugUsartRxDmaFifo, 0, sizeof(s_ulDebugUsartRxDmaFifo)); if (HAL_UARTEx_ReceiveToIdle_DMA(&huart1, s_ulDebugUsartRxDmaFifo, sizeof(s_ulDebugUsartRxDmaFifo)) == HAL_OK) { ret = true; } __DSB(); return ret;}/** * @brief The application entry point. * @retval int */int main(void){ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); /* Enable the CPU Cache */ /* Enable I-Cache---------------------------------------------------------*/ SCB_EnableICache(); /* Enable D-Cache--------------------------------------

Hello everyone.My fight with STM32H7R7 continues.I'm trying to get the simplest example of triggering the EXTI interrupt on an STM32H7R7I8T6. I've run this thousands of times on other H7 series MCUs and never had any problems. I have a button and an LED connected to the MCU as shown in the diagram.Pin PC11 configured as below:/*Configure GPIO pin : PC11 */GPIO_InitStruct.Pin = GPIO_PIN_11;GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;GPIO_InitStruct.Pull = GPIO_NOPULL;HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);/* EXTI interrupt init*/HAL_NVIC_SetPriority(EXTI11_IRQn, 0, 0);HAL_NVIC_EnableIRQ(EXTI11_IRQn); I added to the Callback code as always:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){    if(GPIO_Pin == GPIO_PIN_11)    {        HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_12);    }}/* USER CODE END 4 */ Optionally, I also added lines in the Callback itself:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){ if(GPIO_Pin == GPIO_PIN_11) { HAL_GPIO_Togg

Hello everyone.I'm creating a TouchGFX project for a custom PCB with an STM32H7R7I8T6. After initial compilation issues, I unchecked the "Generate Under Root" option in the project manager and managed to compile the empty project and upload it to the MCU. Now I want to add a driver for the GT911 touch panel. I add one file, gt911.h, to the "Appli/Core/Inc" location, and it's visible, but the gt911.c file in the "Appli/Core/Src" location isn't visible to the project. This is my first time using this project organization and I can't figure it out.Please help.

Hello Team, On the Development Board, pin PN12 is used to detect whether an SD card is inserted or not; however, it is also required by xspm_p2_ncs, so I don’t think we can simultaneously use XSPIM1, XSPIM2, and PN12. Is there any other pin you would recommend for the purpose of detecting an SD card? Also, I am using the mechanical switch to detect the SD card. In the Datasheet, SDMMC1 is specified for the SD card However, in the AN5967 Document, SDMMC2 is preferred for the SD card. Which port, SDMMC1 OR SDMMC2, is preferred for a microSD card? Thanking you 

Hello Everyone,I am aiming to integrate a 64mb NOR Flash non-volatile memory to my stm32n6,However, the recommended models were MX66UW1G45GXDI00 and MX25UM51245GXDI00,They are out of stock on every major electronics market in the world,,are there any legit alternatives to these models , that are compaitable with stm32n6 and serves my need,If so please let me know.Thanking you

Hello everyone , I was reading in the power controller section 5 in RM0368 , I had some difficulties understanding some terms and distinctions and I would like your support please . The main goal ifor me is to  categorize each group of functionalities by their power source as as being Digital VDD , Analog VDDA , VBAT powered . According to figure 7 page 71 :  The analog domain is ADC , RCs and PLLs and .. etc , I would like to know a complete list of the rest of functionalities associated with the analog Domain , Even in DS9716 Page 18 section 3.13 third Bullet it specify a partial list of blocks but it includes “Reset Blocks”  , what does reset block refer to exactly can i conclude safely its the POR , PDR , BOR , PVD blocks exactly or that is not correct or partial .Regarding digital domain the word “digital” does it mean “Digital peripherals” ?  Why “IO Logic” different  from “GPIO peripheral” being a part of digital peripherals ?For VBAT , what is the functionality of “wakeup logic

Hey,I have some questions. First, why does the installer install the app below ~/Library/Application Support?This location is for the support files of an app, not the app itself. The installer, however, puts everything there, including the .app BundleImprovement: Please move the .app Bundle install location to /Applications or ~/Applications. Supporting files then belong in the aforementioned path. Second, why can the .app Bundle not be started on it’s own? When I open it, it loads a splash screen with a progress bar, but when the app windows comes up all it shows is a loading circle. To really start CubeMX2 you HAVE TO use the startup binary which the installer also provides, but there is currently no way to just start the app from the launcher.This is very bad as it goes completely against the way 99% of how Mac users launch apps. CubeMX1 does this correctly, why is that such a step backwards with CubeMX2 ? Because currently, after installing the app there is no way to start it from

IntroductionEmbedded applications are evolving toward increasingly demanding memory requirements. This evolution is due to the growing demand for richer graphics, a wider range of multimedia and other data-intensive content.To address this need, STM32 devices integrate high-speed external memory interfaces that make it possible to add complementary memory suited to memory-intensive applications.This article presents a practical example of configuring the external flash memory MX66UW1G45G on the STM32H7S78-DK via XSPI2.Introduction 1. Project overview 2. Prerequisites 3. Steps Related links1. Project overviewThis project illustrates how to configure the MX66UW1G45G octo-SPI NOR flash memory on the STM32H7S78-DK using the XSPI2 interface. The example configures the memory in Octal DTR mode, performs a sector erase and a page program operation by writing a string into the NOR flash using indirect mode. Finally, it then switches the XSPI peripheral to memory-mapped mode for readback verifi

From my understanding all STM32N6 chips need a external flash chip and there's a static stage 0 boot loader.  So if this is true is there any limitation's on the brands of flash or speed/address bit size limitations? With the previous stage 0 bootloader for a different non ST product had a lot of limitation on the flash that could be used.* 16 bit flash address only* Only support a few brands of flash chips.  

STM32N6: Black screen after HAL_NVIC_SystemReset() — FSBL not booting, works fine after NRST/power cycleGövde:Hello,I have a bootloader (FSBL) and a separate application on anSTM32N645L0, running from external XSPI NOR flash MX25UM25645GXDI00 in memory-mapped XIP mode (Octal DTR).Setup:FSBL configures the external flash into Octal DTR mode (volatile CR) at every boot and shows update/bootloader graphics on the display The application runs its own graphics To enter bootloader mode from the application, call HAL_NVIC_SystemReset()Problem:After HAL_NVIC_SystemReset(), the device stays on a black screen — the FSBL graphics never appear. However, if I reset via the NRST button or a full power cycle, everything boots normally.What I suspect:Since the N6 is flashless, BootROM must read the FSBL from external flash in standard SPI mode. My theory is that after a software reset the flash chip stays in Octal DTR mode (it doesn't lose power), so BootROM cannot read the FSBL at all.Questions:Is th

​After generating a CMAKE project using STM32CubeMX2 v1.1.1 followed by setting compiler options to “treat warnings as errors” (-Werror) and enable strict standards-conformance (-Wpedantic) in the root CMakeLists.txt file, I am errors in, mx_def.h. Though this post shows the workaround:What is the recommended C Standard that STM32C5 project should follow? If the generated code stated “gnu11” but yet uses “gnu23”, shouldn’t the generator use the latter instead (see solution)? And, what are the dangers of doing so? Error Message:error: ISO C restricts enumerator values to range of 'int' before C23 Full Error message:[build] C:/PathTo/ProjectName/source/App/generated/hal/mx_def.h:32:38: error: ISO C restricts enumerator values to range of 'int' before C23 [-Werror=pedantic][build]    32 |   SYSTEM_OK                        = 0xEAEAEAEAU,        /* System initialization successfully       */[build]       |                                      ^~~~~~~~~~~[build] C:/PathTo/ProjectName/source

That pretty much says it all.   Any attempt to tear down the connection (disable spi, disable dma, etc) before (long before) stop1 causes flash write after (many instructions after) the wfi to fail with PGSERR error.   Not tearing down the connection, flash write works, but standby doesn’t without additional work.   To be concrete dma3ChannelFreeI(spip->dmatx); if (spip->state == SPI_READY) { /* Just in case this has been called uncleanly.*/ (void) spi_lld_stop_abort(spip); spip->spi->CFG1 &= ~(SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN); spip->spi->CR1 &= ~SPI_CR1_SPE; /* Releasing DMA channels.*/ dma3ChannelFreeI(spip->dmarx); dma3ChannelFreeI(spip->dmatx); Those two lines -- spip->spi→… are what break flash write.  Clearly there is an undocumented interaction between peripherals and the clock and data transfer system, but the documentation for the part is shockingly incomplete on important details such as this.Leaving those lines out

Hi everyone,I’m working on a small STM32 project using a piezo buzzer and would like to generate a simple melody from different frequency tones.I can already generate individual tones by changing the timer frequency, but I’m not sure what the best approach is for playing a sequence of notes with different durations.For example, I would like to create a short melody such as:Note A → short duration Note B → short duration Note C → longer duration Pause → short duration RepeatWould it be better to use a timer with PWM and change the frequency for each note, or is there another recommended approach for generating melodies on STM32?I’m mainly looking for guidance on the structure of the code and how to handle the note frequency and duration cleanly.Thanks in advance for any suggestions!

I am having an issue with .ioc file association on macOS when using STM32CubeIDE 2.2 together with the standalone STM32CubeMX.The .ioc file does not seem to be properly registered with macOS.For example, in Finder, .ioc files are shown as unknown files rather than as STM32CubeMX project files.More importantly, when I open an .ioc file from STM32CubeIDE, STM32CubeMX is launched, but it stays on the welcome screen instead of opening the selected .ioc project.The behavior is roughly:STM32CubeIDE ↓STM32CubeMX launches ↓CubeMX stays on the welcome screen ↓project.ioc is not opened I've made some checks. macOS does not appear to assign a normal, application-specific UTI to the .ioc file.For example:mdls -name kMDItemContentType -name kMDItemContentTypeTree project.iocreturns:kMDItemContentType = "dyn.ah62d4rv4ge80w55d"kMDItemContentTypeTree = ( "public.item", "dyn.ah62d4rv4ge80w55d", "public.data")I also checked the application bundle:plutil -p /Applications/STM32

Hello everyone,I'm trying to configure the SAI and GPDMA peripherals on an STM32 to acquire audio from an I2S microphone. My goal is to capture a 32-bit, 2-channel audio stream at a 16 kHz sample rate, with the STM32 acting as the clock master. I've followed the steps below, but I'm running into two main issues:While the HAL_SAI_RxCpltCallback and HAL_SAI_RxHalfCpltCallback functions are being called, the acquisition buffer remains unchanged (full of zeros).I'm seeing a 16 kHz signal on all three I2S lines (SCK, FS, and SD), which is incorrect. The clock (SCK) should be much higher.Here's a summary of the steps I've taken:PLL4 Configuration: I've configured PLL4 to generate a 1.024 MHz clock (16 kHz * 64 = 1.024 MHz). This clock feeds into the IC7 peripheral.GPDMA1 Configuration: I've enabled the clock and interrupts for GPDMA1 Channel 0 and added a linked-list initialization.SAI1 Block B1 Configuration: I've set up the SAI handle for I2S standard, 32-bit data, 16 kHz audio frequency,

Hi,I have custom PCB with STM32WB5MMG, which has STM32WB55VGY. I want to update FUS and software stuck and I would like to confirm which start address is the correct one. Should it be the one from the column STM32WB5xxG(1M) (as the chip is STM32WB5MMG) or the one from column STM32WB5xxY(640k) (as the MCU is STM32WB55VGY)?  

Hi.I’m using CubeIDE, CubeMX and HAL to create an application for an STM32L451.I’ve setup USART1 to receive via DMA in circular mode and detect line idle, starting receptions with HAL_UARTEx_ReceiveToIdle_DMA(), and processing receptions in callback HAL_UARTEx_RxEventCallback().All seems to work fine except that the TC (transfer complete, or full buffer) interrupt never happens.HT (half transfer, or half of the buffer reached) and line idle do interrupt.I’m providing HAL_UARTEx_ReceiveToIdle_DMA() a buffer of size 128 bytes. I’m logging the value of the size argument to HAL_UARTEx_RxEventCallback(). When I manually send a message of 20 bytes repeatedly, but slowly enough to ensure line idle triggers, the callback is called with the following size values: 20, 40, 60, 64, 80, 100, 120, 120, 12, 32, 52, 64, 72, 92, 112, 112, 4, 24, (etc).You can see that line idle works, and also that HT is issued in the middle of a reception (size == 64), but TC isn’t, there’s no size equal to 128.What’s

Hi ST Support Team,We encountered a reproducible HardFault when running an object detection model on the STM32N6570-DK, and have completed extensive isolation testing. We believe this points to an issue in the STEdgeAI 4.0.1 / Neural-ART toolchain combined with the Getting Started reference application (concurrent camera/display/NPU usage), rather than a configuration mistake on our side.[Environment]- Board: STM32N6570-DK (with IMX335 camera)- Project: Getting Started Object Detection App (stm32ai-modelzoo-services)- Model: st_yoloxn (1 class, 416x416), Quantized (input: uint8 / output: int8)- Toolchain: STEdgeAI Developer Cloud v4.0.1 (forced by cloud; v4.0.0 is no longer offered, though the project's own README states the shipped model files were generated with v4.0.0)[Symptom]Build, flash, and boot-from-flash all complete without error, but the LCD stays black. Debugging via STM32CubeIDE shows a HardFault during NPU inference:HardFault_Handler()__LL_ATON_RT_IrqErr(irqs)   // ll_ato

Hi, I have a custom product/board that has an embedded STM32L433. The STM32 is powered with an external battery. It is also connect through USB to a COM board that runs Windows. The COM controls the boot0 and reset pins of the STM32 which allows me to update the chip using CubeProgrammer API. I created a custom application in C# that worked fine until I tried to activate RDP level 1. Since I cannot do a POR, I implemented the activation of RDP in the STM32 software using the enter standby mode method. When I try to update with the RDP already active, I use the connectDfuBootloader2 method with rdu = true. This properly downgrade RDP from level 1 to level 0 and I am able to update the STM32 using the downloadFile method afterward. The issue is that after downloading the new software, the STM32 gets stuck in bootloader. The only way to get it unstuck is to call another time the connectDfuBootloader2 with rdu = true. This does not downgrade the RDP level, it only restarts the STM32 which

Hello everyone,I am using STM32F103ZG MCU in a custom board for more than 7 years; 5 years ago, for shortage issues, I change the LSE oscillator from  MC-306 32.768K-E3 (CL=6pF; ESR=50k max) to 9HT10-32.768KAZY-T (CL=7pF; ESR=70k max) and I changed the external CL capacitance from 3.3pF to 10pF. I had no problems for 5 years. Now, in several boards, the LSE clock takes long time to start or even does not start until I “perturb the system” touching the capacitors or the uC’s pins with my finger.Looking at the uC’s datasheets it seems that the feedback resistor of the oscillator’s internal circuitry (don’t know if is a “real” resistor or an equivalent resistance given by the internal circuitry) is 5M but, with indirect measurement, it seems to be much more than 5M (like hundred times more). This is for both the old boards and the “faulty” new ones, so is not (perhaps) an issue caused by the productive process of the uC.As I written before some faulty boards in which the LSE at last start

When building in STM32CubeIDE 2.1.1, and targeting an STM32F303K8,Project properties C/C++ Build Settings MCU GCC Compiler Miscellaneous Near the bottom, observe a checkbox for -mtune=cortex-a35.This option really does have effect in the gcc command line, and that really does significantly alter the compiled machine code.But… why is this allowed in the UI? Why would this tuning option appear specifically for the A35, when the STM32F303K8 is an M4? By default, the makefile does correctly add -mcpu=cortex-m4.

I’m just starting a new project using the STM32H563. It has 16 channels of DMA, 8 in GPDMA1 and 8 in GPDMA2. I have at least 11 peripherals I’d like to use DMA for, UARTs, I2C and CAN. That means 22 channels of DMA if I want to use DMA for RX and TX. Does it make sense, or will it even work to use DMA for the RX side of a UART (for example) and IT for the TX side?My goal is to eliminate or at least minimize blocking in my program. I care more about DMA on the RX side since I often don’t know how many bytes will be in the message from the peripheral. I’ve used character match on the STM32H7A3 to deal with that in the past and the H563 is supposed to support character match also. TX is easier since I always know how many bytes I’m sending. I understand I’m still using CPU cycles to TX in IT mode but I don’t think that will cause any significant issues (I hope).

I’ve been using STM32CubeIDE, STM32CubeMX, STM32CubeProgrammer, and STM32CubeMonitor on a Mac currently running macOS 26.6.When I run env or export in Terminal (which uses Zsh by default), I find these two STM32-related environment variables.STM32CubeMX_PATH=/Applications/STM32CubeMX.app/Contents/ResourcesSTM32_PRG_PATH=/Applications/STM32CubeProgrammer/STM32CubeProgrammer.app/Contents/Resources/binExamined Zsh dotfiles in my home folder and found the following two *export*s in ~/.zshrc that set them.export STM32CubeMX_PATH=/Applications/STM32CubeMX.app/Contents/Resourcesexport STM32_PRG_PATH=/Applications/STM32CubeProgrammer/STM32CubeProgrammer.app/Contents/Resources/binWhich apps have added these; CubeMX, CubeProg, or perhaps the respective plugins from CubeIDE? What is their intended purpose, and in particular, which other STM32Cube tools rely on them? Also, do the apps add these every time on launch or only once during installation?

I am trying to generate an interrupt when the HSP finishes a processing list so that I don’t need to poll it. However, I can’t seem to figure out how to do this.There are some things in the STM32U3 reference manual that make me confused:In section 19.4.12 HSP interrupt controller (HITC), there are four interrupt lines:• An interrupt line handling errors (hsp_err_it)• An interrupt line handling various hardware events (hsp_evt_it)• An interrupt line handling events generated by the SPE processing (hsp_fwevt_it)• A global interrupt is asserted when one of the previous interrupts is asserted (hsp_it)However, in Section 19.3 HSP Implementation, Table 143 shows that neither hsp_err_it, hsp_evt_it, nor hsp_fwevt_it are implemented in the U3 series. If this is the case, does that mean that hsp_it is just never asserted? Is it possible to notify the application when a processing list has finished without polling for a flag?Section 5.13.5 of UM3360: HSP processing functions says that the SET_FL

Hello everyone,I am trying to use TLS 1.3 with Mbed TLS on an STM32H573 through the Secure Manager’s Global PSA API.At the moment, I am seeing the following errors: psa_sign_hash() / psa_sign_message()→ PSA_ERROR_NOT_PERMITTEDpsa_generate_key() / psa_import_key()→ PSA_ERROR_GENERIC_ERRORThe persistent ECC keys are provisioned with the required signing permissions, and both the Secure Manager and the non-secure application start correctly.Some TLS 1.3 HKDF operations had to be implemented locally because the PSA Crypto API version in use is 1.0 and does not provide separate HKDF-Extract and HKDF-Expand algorithms.My questions are:Are persistent ECC keys supported with psa_sign_hash() through the Global PSA API? Does the Secure Manager support volatile keys with psa_generate_key() and psa_import_key()? Are additional permissions or a Secure Module required? Is there a support matrix or an official TLS 1.3 example for this setup? Does anyone have experience with Secure Manager and MbedTLS