Recently active topics

As per the subject line, is there a way to derive keys from a symmetric master key stored in a slot of an STSAFE-A120, using the `stselib` included in the X-CUBE-STSE-01 software package? Thanks,Giorgio.

Hi everyone,I want to read data from an SPI slave using SPI3 while the MCU is in STOP2 mode.The communication protocol requires me to transmit a command before receiving the response.I configured LPBAM according to the following YouTube tutorial, and my CubeMX/LPBAM configuration is shown in the attached screenshots.My observations are:If I use only the “Transmit Data” node, everything works correctly. If I add a “Receive Data” node after the transmit node, the SPI transaction stops when it reaches the receive node. However, the “LPTIM1_CH1” output continues to generate trigger signals. If I replace them with a single “Transmit Receive Data” node, neither SPI nor LPTIM1_CH1 works.Could you please explain what might be causing this behavior? Is there any additional configuration required to use the “Transmit Receive Data” node in LPBAM with SPI3 in STOP2 mode?Thank you. 

Hello,I am currently developing a USB Device application using the STM32N657L0.I am reaching out to ask for advice because I am having difficulty meeting the target power consumption requirement of 5V, 2mA max during USB Suspend state. Our target conditions and system requirements are as follows:VDDCORE uses an external power supply. The USB Driver must be maintained during USB Suspend. The system must be able to wake up and recover via USB. Power consumption must remain below 5V, 2mA during USB Suspend.Currently, when the chip is configured in STOP Mode, the measured power consumption is:VDDA18AON (1.8V): ~5mA VDDCORE (0.81V): ~40mA We are looking for ways to further reduce these currents to meet the 2mA requirement.Could you please guide us on how to optimize the power modes, clock gating, or power supply configurations to achieve this? Any suggestions or reference guidelines would be greatly appreciated.Thank you for your support.Best regards,

Please can anyone help, I am trying to upload an avatar to my profile, every time I try I get an error message:-“Connection timed out. Please try again or use a smaller image” I have tried on mobile phone and Chrome desktop same error and tried with different small files without success. 

Hi everyone,While using the comparator interrupt functionality, I discovered an error in the comparator block diagram provided in the Reference Manual for the H723 series(RM0468):As shown in the image above, the signal that triggers the interrupt does not actually pass through the polarity selection stage; instead, it is routed to the interrupt logic immediately after the comparator output. My evidence is as follows:First, I observed that a specific output state causes the interrupt to trigger continuously (making it impossible to clear the `CC1IF` flag). Upon checking the block diagram, I saw that `CC1IF = cmp1_out & ITEN`, which implies that setting `cmp1_out` to 0 should resolve the issue. However, in practice, this has no effect—the `CC1IF` flag remains set. The only way to clear `CC1IF` is to adjust the comparator inputs to invert the comparator's output.These are the results I obtained from testing on an STM32H723ZGT6.

There are still some typos to fix in the migration docum. for instance:"Atomic" API names - change to "unitary" as was agreedPACKET - > PACKED 

Hi ST,I have developed and manufactured a custom STM32WL55CCU6 target based board, based on the reference board STDES-WL5U4SBB you provided, and I noticed the following issue:when I uploaded my application that I have uploaded and tested before on the NUCLEO-WL55JC1 Board with region configuration LORAMAC_REGION_US915, I found that the gateway receives only on the uplink sub-channel Band 64 which has a bandwidth 500KHz, although the same application uploaded and executed successfully on the board NUCLEO-WL55JC1 and connected with all other sub-channel Bands with band width 125KHz.In the Board NUCLEO-WL55JC1 based on the target STM32WL55JC17 I Found in the schematic that it has 2 External Oscillators: (TCXO 32MHz and the default HSE 32MHz Oscillators) and the application running on the NUCLEO-WL55JC1 used the TCXO Oscillator, while the other board I developed based on the STDES-WL5U4SBB board has no TCXO (as the reference provided) So my questions are:Q1: What could be the reason of thi

When I started working with NUCLEO boards I was very cautious about powering the board up from 5V let alone 12V even powering the board via STLINK USB at 5V (maybe as much as 250mA)So I did some reading. On my NUCLEO-H5E5ZJ :-The buck regulator ST1S40IPUR  (U16) becomes transparent at under 5V - it just conducts The linear regulator for main 3V3 is LD39200PU33R (U15) and has very low dropout  Most of the STM32H5E5 pins have Absolute Max tolerance rated at 4V If not being used I could put the STLINK into reset via a jumper (less current to board) Avoid initial connection of Ethernet cable or any USBI tried feeding just under 4V limited to 150mA max into the buck regulator and still got 3.3 Volts out of U15.  The MCU runs fine and I can boot it using USART1. I haven’t learned how to use STLINK just yet :)For my board with STLINK in reset the Ethernet PHY current about 45mA and total current was 95mA on wakeup and 115mA in bootstrap.Why do this, well if I short more than 4V to any port pi

Dear STMicroelectronics Support Team,We are currently investigating a potential EEPROM data integrity issue involving the M95320-A125/A145, and we would appreciate your urgent technical guidance.Our product is already deployed in the field, making this issue particularly critical.1. Application and Write ScenarioOur application uses the M95320 EEPROM, and we repeatedly write data to address 0x1CF.The relevant ECC group is 0x1CC–0x1CF, as described in the Error Correction Code (ECC × 4) section of the datasheet.Our SPI trace confirms that the application sends a single data byte when writing to address 0x1CF. We do not explicitly write to the other three addresses in this ECC group.The relevant SPI transaction is:MOSI: 02 01 CF F8Where: 0x02: WRITE instruction 0x01CF: Starting address 0xF8: Single data byte According to the datasheet, although a single byte can be written independently, the other three bytes in the same ECC group are also affected in terms of write cycling.2. Applic

I'm using SPI1 on an STM32H5E5 in slave mode, with DSIZE = 32 bits, TSIZE=0 and `FTHLV` configured for four 32-bit frames.I'm trying to understand the internal transmit pipeline more precisely.Is the internal TX shift-register width (in bits) or transfer granularity documented anywhere for the STM32H5E5 please?What is the effective width of the TX shift register, and how does data move from the byte-organised TX FIFO into it?I would appreciate clarification of the internal TX FIFO to TX shift register data flow please?For a 16 byte Tx FIFO, assume the TX FIFO is pre filled and full, as transmission begins, data transfers from the TX FIFO into the TX shift register so the Tx FIFO has new space immediately. So the TX FIFO becomes empty before the RX FIFO becomes full. What I'm trying to discover is how many SCLK pulses occur between TX FIFO empty and RX FIFO full. I expected it to be around 32 SCLK's (32 bit) but its closer to 8 SCLK's closer to one byte rather than one word.Any informat

Heyho,just when we got the quote from our PCB assembly company for a prototype of a big board with the STM32H733, I find that basically all HyperRam ICs with 3.3V are EOL. There’s no alternative to 8-pin HyperRam due to IOs, routing, and board space, so the best would be to switch the complete system from 3.3 V to 1.8 V.BTW, I find that the HyperRams are working great with the H7, 11 IOs, only, fast, relatively low power, no problems at all so far.It’s 2026, darn… I started working as an EE at around 2000, and then the 5V → 3.3V transition was mostly done. Now it’s time for 1.8 V.Anyway, I checked the H73x datasheets, and looks like these are fully operable at 1.8V without any problems (only exception: the internal OPAMP needs >= 2.0V, but we don’t use that), at full clock and IO speed.So my questions to the H723..H735 users:Anything I did oversee or forgot ? What’s your experience running the H7 at 1.8 V ?Changing the rest of the components is another … PITA, but first I need to kn

I am using custom board that only has STM32WBA65CIU6 and IIS3DWB. I am using STM32CubeIDE v2.2.0, STM32CubeMX v6.18.1, and STM32Cube FW_WBA V1.10.0.I generated a project from CubeMX with the default configurations without changing or enabling anything except1) Enable ICACHE 2-way2) Enable HSE and LSE, use SMPS and turn off prefetch3) Enable SRAM1 and SRAM2to match the conditions mentioned in the datasheet for the current charactersticsI tried in an empty code, just the generated initialization from CubeMx and empty while(1)1) Using HSE + PLL to have 100MHz HCLK and read 3.39 mA which is fine2) Using HSE only to have 32MHz HCLK and read 2.27 mA which is above the 1.7 mA3) Using HSI only to have 16MHz HCLK and read 1.53 mA which is above the 0.46 mAWhen I try entering any low power mode, I read 0.87 mA which is much higher than expected.I tried disabling the RAMs and the ICACHE, disabling the HSE and the LSE, set ULPMEN to 1 and leave it, and other many cases and still get the same 0.87

I am following https://www.st.com/resource/en/product_presentation/evlspin32g4-act-and-stwinbox-high-speed-datalogging-for-motor-control-and-sensors-quick-start-guide.pdf using hardware STEVAL-STWINBX1+EVLSPIN32G4-ACT  https://github.com/STMicroelectronics/stdatalog-pysdk.git v1.5.0 stdatalog_MC_GUI.py is able to start/stop the motor operated in sensorless mode, correct GUI view and .dat file stored for all onboard sensors. But enabling slow/fast motor telemetries leads to error message: “HSDatalogApp.stdatalog_gui.HSD_GUI.HSD_Controller - ERROR - No data from fast_mc_telemetries Component.” For suggestion “Restart the acquisition lowering component ODR to acquire data correctly.”, I tried to only enable one data item in slow telemetry, and had the same failure. FW build env for both PMSM and STWIN.box:MotorControl Workbench_6.3.0 STMCubeIDE 2.1.1 STMCubeMX 6.12 STM32 FW V1.5.2 When importing the STWIN.box FW project, among three projects(DATALOGMC, DATALOGMC_CubeAI, DATALOGMC_NanoEdge

Hi,I am currently using ST’s OpenSTLinux distribution, version 6.2.1, for our STM32MP135F-based custom board.My objective is to customize the boot and operating system components—TF-A, OP-TEE, U-Boot, and the Linux kernel—to meet our board-specific requirements. Boot media is emmc.I have successfully set up the Yocto build environment and can build the complete image. However, to reduce development and debugging time, I would like to build these components individually rather than rebuilding the entire image after every change.I have also set up the environment for building and installing these boot artifacts separately. I would appreciate your guidance on the correct build and deployment sequence, including which source files, configuration files, device trees, and generated binaries are required at each stage.Could you please clarify the recommended workflow for building, integrating, and flashing TF-A, OP-TEE, U-Boot, and Linux independently while ensuring compatibility with ST’s Op

Hello,I am using an STM32N657 on a custom board.I need to use PA6 as PIXCLK, so I would like to move the BOOT1 function from the default PA6 pin to PN10.According to the STM32N6 BootROM/OTP description, I understood that BOOT1 can be remapped using OTP19 (BOOTROM_CONFIG_10): I programmed OTP19 with 0x15200000 in STM32CubeProgrammer to change BOOT1 from PA6 to PN10.Before programming OTP19, I could connect to the MCU normally through ST-LINK/SWD using PA6 as BOOT1.However, after programming OTP19 to 0x15200000, I can no longer connect to the MCU.The same issue has occurred on more than one custom board.My test conditions are:MCU: STM32N657 I/O supply voltage: 1.8 V BOOT1 remapped to: PN10 OTP19 programmed value: 0x15200000 PN10 is held HIGH before and during reset ST-LINK detects the target voltage During connection, STM32CubeProgrammer can sometimes identify Device ID 0x486, but then reports that the connection to device 0x486 is lost The board works and SWD connection is available bef

Host MCU: STM32G491METx, FreeRTOS, SPI host interface (SPI_RDY on EXTI, CHIP_EN controlled by host) Module: ST67W611M1, T01 binary (LwIP offload profile) Host middleware: X-CUBE-ST67W61, ST67W6X Network Driver v1.3.0 Clock: W6X_CLOCK_MODE = 1 (internal RC); W6X_POWER_SAVE_AUTO = 0 (also tested with 1; the driver disables it in W6X_Ble_Init because of the RC clock) BLE only, no Wi-Fi in useUse caseThe module is used only as a BLE observer. It continuously scans for manufacturer-data advertisements from 2 ble devices, among a crowded environment (40+ devices around).W6X_Ble_Init(W6X_BLE_MODE_DUAL, …) W6X_Ble_SetScanParam(ACTIVE, PUBLIC_ADDR, FILTER_ALLOW_ALL, interval 105 (65.6 ms), window 104 (65 ms)) W6X_Ble_StartScan(cb) W61_BLE_SCAN_TIMEOUT reduced from 5000 to 1000 ms, and W61_BLE_MAX_DETECTED_PERIPHERAL = 40 On every scan-done callback the application calls W6X_Ble_StopScan() and then W6X_Ble_StartScan() immediately. This gives one stop/start cycle every ~0.35–1 s, i.e. thousands o

Hello ST Team,We have a custom STM32N657Z0H3Q board on which BOOT1 is routed to PN10 instead of the default PA6.To configure the Boot ROM to sample BOOT1 from PN10, we programmed OTP Word 19 (BOOTROM_CONFIG_10) as described in RM0486 Rev. 4, Section 5, Table 18:dev_boot_port [24:21] = 9 → Bank N (PN) → 9 << 21 = 0x01200000 dev_boot_pin [28:25] = 10 → Pin 10 → 10 << 25 = 0x14000000 OTP19 = 0x15200000Steps FollowedBefore programming, we read OTP through SWD. OTP19 was 0x00000000, with status 0x00000000, indicating that it was unprogrammed and not write-locked. SWD/ST-LINK access was working normally. We programmed OTP19 with 0x15200000 using STM32CubeProgrammer v2.23.0, without enabling the lock option. The tool reported: "OTP words programming done successfully"   After the next power cycle/reboot, the device no longer enters Development Boot. Instead, it boots from Flash, and our FSBL and application start running normally. SWD/debug access is no longer available.Same

Dear Sir,We are evaluating the VN9E30F, a 6-channel automotive high-side driver with a 24-bit SPI interface. Kindly clarify whether the IC provides real-time switching status or feedback through a register that can be read via SPI.Also, please confirm the current availability and supply status of this IC.Thank you.

When trying to login to st.cm gives error 

Hello,is it possible to get markdown format of the Reference Manual instead of the PDF version? I do not mean the converted PDF into markdown by MarkItDown or Panda, etc. These tools usually fail when the huge document is processed. They cannot keep the formatting.Why I need it? I want to generate list of typos, misleading information, statements, etc. that should normally be fixed by ST but probably the documentary department is out of the tokens :). E.g. in the sentence in the ADC4 chapter:the end of sequence (EOCSEQ) occurs once the sequence of oversampledcompleted (i.e. after N x sequence length conversions total)I spent time searching for EOCSEQ flag to detect that there is no such a flag and to discover that people writing chapter 34.4.26 were not the same as those writing 34.7 to unify the names  EOCSEQ = EOS. Cheers,Martin  

Hello,We are designing a PCB around the STM32N657B0 (VFBGA198) using the internal SMPS. VDDSMPS and VDDA18PMU are fed from a dedicated 1.8 V buck, with VDDA18PMU filtered from the same rail, as per Figure 2 in DS14791.For our derating and fault analysis we need the absolute maximum ratings of these two pins, and we cannot find them in any current ST document:DS14791 Rev 11 (Sep 2026), Table 22 “Voltage characteristics”: no VDDSMPS or VDDA18PMU row. The “VDDA18 – VSS, 1.98 V” row lists only VDDA18PLL, VDDA18CSI, VDDA18USB and VDDA18ADC. DS14791 Rev 11, Table 25 “General operating conditions”: VDDSMPS and VDDA18PMU are 1.62 / 1.8 / 1.89 V. DS14791 Rev 11, Table 29 “Characteristics of SMPS step-down”: the input is called “VDDA18”, 1.62 to 1.89 V. AN5967 Rev 6, AN6000 Rev 1 and RM0486 Rev 4: no absolute maximum for either pin.QuestionsWhat are the absolute maximum ratings (min and max) for VDDSMPS and VDDA18PMU? Does the “VDDA18 – VSS, 1.98 V” row in Table 22 also cover VDDSMPS and VDDA18P

Hello,Our STM32N657 appears to be revision B. We use a battery-powered board with an STM6601 power-button controller. The MCU asserts PSHOLD early in the FSBL to keep power enabled.ES0620, section 2.2.18 specifies setting SYSCFG_CM55RSTCR.CORE_RESET_TYPE, followed by a software reset (NVIC_SystemReset()), after the first power-on reset.That additional reset conflicts with our power-hold arrangement.Is the initial software reset strictly required for the NRST workaround, or can we set CORE_RESET_TYPE and continue booting? If it is mandatory, is there a supported alternative that avoids this extra reset?Thanks!

Hi Folks,I was working on Secure Boot for the STM32H533, following the documented steps for the STiRoT boot path. I used the STiRoT boot path based on the STM32 documentation.https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_STM32CubeMX_STiRoT_Boot_path_on_STM32H57 I am trying to bring the device back to the OPEN state, but I am facing an issue during the process. After providing the Key File Path and Certificate and selecting Full Regression permission, the Debug Authentication step fails.16:42:50:983 : Start Debug Authentication Sequence16:42:50:984 : SDMOpen                       :   765 : open       : SDM API v1.016:42:50:985 : SDMOpen                       :   766 : open       : SDM Library version v1.4.016:42:50:986 : open_comms                    :   606 : open       : Asserting target reset16:42:50:987 : open_comms                    :   614 : open       : Writing magic number16:42:50:987 : open_comms                    :   678 : open       : De-asserting target rese

I am observing that some of the #defines are not highlighted in blue color in STM32 Cube IDE, some are highlighted. What is the reason? It is bit inconvenient if it is not highlighted.

Subject: STM32F373CCT6 SDADC: Wrong Readings with VDDA Reference on One Board After Environmental TestingHello ST Support Team,We use the STM32F373CCT6 to read four analog inputs with SDADC1 and SDADC2. One of our boards developed a problem during environmental testing (temperature change, dry heat, cold, damp heat cyclic and steady state), where it ran in full-function mode throughout.What happenedThe board worked correctly until day 2 of the damp heat steady-state test (40 °C). Then all four channels read with an offset (for example, a 100 V input read as 50 V). After a power cycle it worked for 2 to 3 hours, then read full scale (3.3 V) even with no input. Reflashing the firmware did not help.A couple of days later we debugged it with the same firmware (internal VDDA reference). With no input, each channel should read 1.65 V (confirmed with a multimeter at the MCU pin), but the firmware reads 1.85 V on all four channels. With the reference set to internal 1.8 V, the readings are cor