Inquiry regarding Power Consumption Optimization in USB Suspend Mode for STM32N657L0

[brenda00]

Hello,

I am currently developing a USB Device application using the STM32N657L0.

I am reaching out to ask for advice because I am having difficulty meeting the target power consumption requirement of 5V, 2mA max during USB Suspend state.

 

Our target conditions and system requirements are as follows:

1. VDDCORE uses an external power supply.
2. The USB Driver must be maintained during USB Suspend.
3. The system must be able to wake up and recover via USB.
4. Power consumption must remain below 5V, 2mA during USB Suspend.

Currently, when the chip is configured in STOP Mode, the measured power consumption is:

1. VDDA18AON (1.8V): ~5mA
2. VDDCORE (0.81V): ~40mA

 

We are looking for ways to further reduce these currents to meet the 2mA requirement.

Could you please guide us on how to optimize the power modes, clock gating, or power supply configurations to achieve this? Any suggestions or reference guidelines would be greatly appreciated.

Thank you for your support.

Best regards,

[FBL]

Hi ​@brenda00 

Can you share schematics? Did you try to reproduce using reference board?

[brenda00]

Hello,

Thank you for your response. Please find our feedback on the items below:

1. We have not yet tested this on the Reference Board(NUCLEO-N657X0-Q).

2. We replaced the STM32N657L0 with the STM32N655L0 and tested it, but observed the same results:

   • VDDA18AON (1.8V): ~5mA

   • VDDCORE (0.81V): ~40mA

3. Please understand that we cannot share the full schematic due to confidentiality. Instead, I have attached key excerpts of the relevant schematic sections.

Please let us know if you need any additional details based on the provided circuit snippets.

Best regards,

[FBL]

Hi ​@brenda00 

USB Suspend is a USB protocol state; Stop mode is an MCU power mode.

USB suspend current limit applies to current the USB function draws from VBUS, not automatically to the sum of current measured on every MCU rail. I assume it is specified in the ECN to USB2.0 specifications, “the suspend current must not be higher than 2.5 mA.”

[brenda00]

Hello FBL,

Thank you for your quick response and guidance.

Since our system operates directly on VBUS power, the current measured at VBUS reflects the total consumption, including the MCU's current during STOP MODE. This is why we measured and analyzed the individual current draw for each MCU power rail.

Thank you once again for your assistance.

Best regards,

[FBL]

Hi ​@brenda00 

The datasheet specifies Stop mode current supply rails under these defined conditions. Based on the measured rail voltages and currents, the combined power is approximately 41.4 mW. If this power is supplied from USB VBUS, it corresponds to at least 8.3 mA at 5 V under ideal conditions , so a 2 mA VBUS target would not be achievable in that configuration. In general, it is recommended to put unused GPIOs in analog mode and disable peripheral and bus clocks that are not needed based on your application.

 

[brenda00]

Hello FBL,

Thank you for your response and for sharing the data table.

Based on the typical values provided in the table, the power consumption is calculated as follows:

• IDDCORE: 9.06mA @ 0.81V(SVOS HIGH) → 7.3386mW

• IDD: 0.2734mA @ 1.8V → 0.49121mW

• IDDA1V8: 0.0617mA @ 1.8V → 0.11106mW

• IDDA1V8AON: 0.0417mA @ 1.8V → 0.07506mW

This sums up to a total of 8.01593mW, which translates to approximately 1.603mA at 5V.

While we understand that achieving these ideal values in a real hardware setup can be challenging, our application strictly requires us to get as close to this reference estimate as possible.

We would greatly appreciate your continued guidance and recommendations on how we can optimize our setup to approach these numbers.

Thank you once again for your support.

Best regards,

[FBL]

Hi ​@brenda00 

You can start with this example STM32CubeN6/Projects/NUCLEO-N657X0-Q/Examples/PWR/PWR_STOP  This should be optimized. In the USB core, set STPPCLK; set GATEHCLK if OTG register access is not needed while suspended. You can also check in the reference manual Table 74. Peripheral clock enabling.

[brenda00]

Hello FBL,

Thank you for your response.

Our system firmware architecture consists of FSBL and APP. Below is the current implementation of our STOP Mode entry and exit sequence:

static void _usb_stopmode_idle(void)

{

    HAL_DBGMCU_DisableDBGStopMode();

    __HAL_RCC_BSEC_CLK_ENABLE();

 

    USB1_OTG_HS->GAHBCFG |= USB_OTG_GAHBCFG_GINT;

    USB1_OTG_HS->GINTMSK |= USB_OTG_GINTMSK_WUIM;

 

    SET_BIT(IBK_USB_OTG_PCGCCTL, USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK | USB_OTG_PCGCCTL_PHYSUSP);

 

    SET_BIT(USB1_HS_PHYC->USBPHYC_CR, USB_USBPHYC_CR_RETENABLEN1 | USB_USBPHYC_CR_AUTORSMENB1);

 

    HAL_PWREx_ControlStopModeVoltageScaling(PWR_REGULATOR_STOP_VOLTAGE_SCALE3);

 

    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

    RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK);

    RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI;

    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;

    HAL_RCC_ClockConfig(&RCC_ClkInitStruct);

 

    __disable_irq();

 

    HAL_SuspendTick();

    SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);

    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;

 

    __HAL_PWR_CLEAR_FLAG(PWR_FLAG_STOPF);

    HAL_NVIC_ClearPendingIRQ(USB1_OTG_HS_IRQn);

            

    HAL_PWR_EnterSTOPMode(0U, PWR_STOPENTRY_WFI);

 

     /* ========================================================= */

 

     __HAL_PWR_CLEAR_FLAG(PWR_FLAG_STOPF);

 

     HAL_NVIC_ClearPendingIRQ(USB1_OTG_HS_IRQn);

     SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);

 

     HAL_ResumeTick();

 

     StopMode_ClockRestore();

 

    CLEAR_BIT(USB1_HS_PHYC->USBPHYC_CR, USB_USBPHYC_CR_RETENABLEN1 | USB_USBPHYC_CR_AUTORSMENB1);

       

   CLEAR_BIT(IBK_USB_OTG_PCGCCTL, USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK | USB_OTG_PCGCCTL_PHYSUSP);

 

   SystemCoreClockUpdate();

   (void)HAL_InitTick(uwTickPrio);

 

   __enable_irq();

}

 

void StopMode_ClockRestore(void)

{

        HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);

        while ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == 0U) { __NOP(); }

        for (volatile uint32_t i = 0; i < 10000; i++) { __NOP(); }

 

        RCC->CSR = RCC_CSR_HSEONS;

        while ((RCC->SR & RCC_SR_HSERDY) == 0U) { __NOP(); }

        for (volatile uint32_t i = 0; i < 300000; i++) { __NOP(); }

       

        MODIFY_REG(RCC->PLL1CFGR1, (RCC_PLL1CFGR1_PLL1DIVM_Msk | RCC_PLL1CFGR1_PLL1SEL_Msk), ((1U << RCC_PLL1CFGR1_PLL1DIVM_Pos) | RCC_PLLSOURCE_HSE));

        RCC->PLL1CFGR3 |= RCC_PLL1CFGR3_PLL1PDIVEN;

        RCC->CSR = RCC_CSR_PLL1ONS;

        /* Hanging point: PLL1 Ready bit does not set */

        while ((RCC->SR & RCC_SR_PLL1RDY) == 0U) { __NOP(); }

 

        __DSB();

        __ISB();

       

       MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_CPUSW_Msk | RCC_CFGR1_SYSSW_Msk),                                 (RCC_CPUCLKSOURCE_IC1 | RCC_SYSCLKSOURCE_IC2_IC6_IC11));

 

       while (((RCC->CFGR1 & RCC_CFGR1_CPUSWS_Msk) != RCC_CFGR1_CPUSWS_0) || ((RCC->CFGR1 & RCC_CFGR1_SYSSWS_Msk) != RCC_CFGR1_SYSSWS_0))

{

                __NOP();

}

 

        PeriphCommonClock_Config();

}

 

Currently:

When entering STOP Mode, the measured power consumption is around 5V, 9mA.

However, upon wake-up, the code gets stuck in IBK_StopMode_ClockRestore() because PLL1 fails to lock (RCC_SR_PLL1RDY is not set).

Could you please advise if there are specific requirements for restoring VOS (Voltage Scaling) or re-enabling PLL1/HSE after exiting STOP Mode on the STM32N6 series?

 

Thank you for your support.

Best regards,

 

[FBL]

Hi ​@brenda00 

The RM states that when the device exits STOP mode, the system clock is initially enabled and switched in Run mode under the HSI clock.
After that, the frequency can be increased again by enabling the PLL, and only once PLL1 is locked that is, when PLL1RDY is set in RCC_SR_PLL1RDY can the system clock be switched back to PLL1.
You can follow the example provided here. SYSCLKConfig_STOP() calls SystemClock_Config(). The configuration restores run  mode VOS using  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1)  before configuring PLL1 and switching the clocks.