STM32 MPUs

The STM32MP2 supports gstreamer. There is a version of Gstreamer for streaming through the WebRTC protocol.Another library for streaming though the WebRTC protocol would be LibWebRTC.My question is if the STM32MP2 have support for LibWebRTC as well?  Thank you for your reply

Hello ST Team,I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33? Is there any official resource ownership matrix available for STM32MP257F? Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33? Are there any peripherals that are exclusively accessible by one core and cannot be reassigned? How is ownership handled for the following peripherals? GPIO Ethernet MACs USB2.0 / USB3.0 FDCAN I2C SPI / OCTOSPI UART / USART SDMMC DDR Controller GPU / VPU / NPU LTDC / DSI / LVDS ADC / DAC Timers DMA / GPDMA Is there a document showing: Peripheral-to-core mapping Security attribution Trust

Evaluation of Display GRAM FunctionalityThe STM32MP157F-DK2 development board is equipped with an OTM8009A display.Link:Display panels hardware components - stm32mpuThis IC includes GRAM storage, which theoretically supports maintaining the display output even after the MPU enters sleep mode.Are there any available test results or evaluation conclusions regarding this?

​@Erwan SZYMANSKI, we are about to design a new hardware based on MP2.Is REV Y ETH1 port stable when used in RGMII mode?Is this config recommended?ETH1 in RGMII mode and ETH2 in RMII

According to the STM32MP257 datasheet:"1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY" "1× PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)"I would like to clarify:Can the USB3DR peripheral be used as a USB 3.0 SuperSpeed port while simultaneously supporting USB 2.0 High-Speed operation on the same connector? Is the embedded USB 2.0 PHY always available when the USB3DR interface is enabled? When PCIe is not used, can the USB3DR interface provide both the 480 Mbit/s USB 2.0 and 5 Gbit/s USB 3.0 links together as a standard USB 3.x port? Is the PHY sharing limitation only between PCIe and USB 3.0 SuperSpeed, or does it also affect USB 2.0 functionality?Any clarification on the USB/PCIe PHY sharing architecture would be appreciated.

Hello, I’m trying to initially build the Distribution-Package 6.2.0 (v26.02.18) as stated in the Wiki (https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package#Initializing_the_OpenEmbedded_build_environment)I am using a VM in Virtual Box running Ubuntu 24.04.5 LTS.I attached the log file.Any help is appreciated :)Thanks in advance.Ben

Hey, Guys!I’m designing an application to record TDM data source with 48k x 16 slots x 32Bit Format based on STM32MP151.But from the datasheet, there is some confusion.It seems the SAI supports 32bit and 16 slots from the SAI main feature description. But the FRL register is limited to 256, which cannot meet the requirement: 32*16 = 512 > 256.I’m using an external CODEC to generate the TDM clock, so STM32MP151 is in slave mode.Does anyone have experience with an application like this?Thanks!      Jampa.    

I have heard that ST have tried QtNanoBrowser on the MP257 and according to them the web browser is working well.My question is if there are any more additional information about the user experience of QtNanoBrowser on the MP257?For example a benchmark and which pages did run smoothly and which pages took long time to load.

Hi,I'm working on a custom STM32MP157C board with a Microchip LAN8742A PHY (RMII). Originally the board uses an external 50 MHz oscillator that feeds both the PHY and the SoC's PA1 (ETH1_RMII_REF_CLK) — the classic LAN8742A "REF_CLK In Mode" setup, same as ST's reference schematic. That works fine.I'm now trying to get rid of the external oscillator and have the SoC generate the 50 MHz REF_CLK itself instead, using RCC's CLK_ETH_PLL3Q — the setup ST documents in AN5031, Figure 45 ("RCC provides 50 MHz ETH_CLK"). For this test I desoldered the two series resistors that fed the oscillator signal in, isolated the oscillator, and bridged PA1 straight to the PHY's XTAL1/CLKIN through a wire + the same 22 Ω resistor as before. I also added st,eth-ref-clk-sel; to the ethernet node in both the kernel and U-Boot device trees, rebuilt and reflashed.Result: PHY never comes out of reset (phy_poll_reset failed: -110), and an oscilloscope on PA1 shows absolutely nothing — not even a weak or distorte

Hello ST team,I noticed what appears to be a documentation typo in the STM32MPU Wiki page “How to configure TSN switch”, section 3.1 – Run the PTP stack.The documentation states:“dePTP stack is started by default. To start it using via systemctl:”but the command shown immediately after that sentence is:systemctl stop deptpI believe the intended command is:systemctl start deptpThis is also consistent with the later “How to trace the PTP stack” section of the same page, where the documentation correctly uses:systemctl stop deptpto stop the service, and:systemctl start deptpto start it again.The Qbv section also states that gPTP synchronization should be started beforehand and thatdeptpis started by default.Could you please confirm and correct the command in section 3.1 if this is indeed a documentation typo?Thank you.

Hi listI am testing the STM32MP135d-odyssey for a project. It is small, still cheap, has support for POE and on board ethernet connectors and SD-card holder. The buildroot repositories are quite old so I wonder if the board is in actual use and can be recommended for new projects?The xogium repository seems very outdated but I have cherry picked a few patches from there to a fork of STMicroelectronics repository and it builds and boots with modern buildroot. I have only tested to boot from sd-card yet.Please test if interested. I have updated versions of buildroot-stm32mp135d-odyssey, u-boot and optee_os in my Github repository.https://github.com/GauiStori/buildroot-stm32mp135d-odysseyShall I make pull requests for u-boot and optee_os to STMicroelectronics or xogium? Or is there an updated version of xogium somewhere?Now I want to see if I can find a working Yocto recipe. RegardsGudjon 

Greetings,I’m working on a STM32MP13X based development board as a learning project. One of the things I’m trying to achieve is a BIOS-like program stored in a NOR flash from which the MPU will boot from every time.After that, the program will load details of any relevant peripherals, Like size & configuration of the installed DDR3 memory & any bootable media like USB drive or SD card. After which the program will boot the bootable media (if any).The aim is to keep the system flexible like a general purpose computer, i.e. no fixed DTS configurations like DDR size, etc in U-Boot or Linux, So that any Linux distro with kernel support for STM32MP1 can be booted off the media.Is this possible? If so, then can you give me an overview of how this may be achieved? I understand this is alot of work which I am willing to do if someone can point me in the right direction.Regards,Aditya M.

Hi everyone,I'm using STM32MP2 OpenSTLinux 6.6 Yocto Scarthgap MPU v24.11.06 with Linux kernel 6.6.48.I am trying to interface a Waveshare LVDS 10.1" FT5x06 touch display with the STM32MP257F-DK. We designed a custom PCB for the required pin mapping. 1. Display :Initially, the display was not working with the original compatible string. After changing the panel compatible to "panel-lvds" only then display started working. panel_lvds: panel-lvds { compatible = "panel-lvds";... /*compatible = "edt,etml0700z9ndha", "panel-lvds";*/ }  2. I2C Touch / HDMI Address :The FT5x06 touch controller uses I2C address 0x38.The ADV7535 HDMI device also uses 0x38 as one of its register-map addresses. Since I am not using HDMI for this test, I changed that ADV7535 address from 0x38 to 0x39:&i2c2 { adv7535: hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>, <0x3c>, <0x3f>, <0x39>; //<0x38>; } ili2511: ili2511@41 { compatible = "ilitek,ili251x

Can the STM32MP231 simultaneously capture or stream four 2-lane MIPI CSI-2 camera streams through a DS90UB960/TDES960 using VC0–VC3?I have reviewed ST’s documentation on “How to use one or multiple multi-stream MIPI CSI cameras.” But did not get complete clarity on simultaneous capture of four camera streams. The documentation example appears to show routing for up to three streams/channels through the DCMIPP pipes (Dump, Main, and Aux).

Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23? Is this specified in any documentation?

Hello Team,We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:Will this impact DDR functionality, signal integrity, or overall system reliability? Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?Your confirmation and guidance will help us proceed with confidence before finalizing the board design.DDR Routing imageMeasuring toolLayer Stack-up 

Hello,I’ve migrated from sdk V25.06.11 to sdk V26.06.10 to compile FIP, tfa, boot and kernel for STM32MP257F-DK board.While the scripts “make_mp2_FIP.sh” and “make_mp2_KERNEL.sh” were working properly with sdk V25.06.11, the script “make_mp2_FIP.sh” hangs nows in the middle of the compilation with an error “ LDS     /Documents/STM32_packages/Sources_v26.06.10/stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sources/ostl-linux/tf-a-stm32mp-v2.10.24-stm32mp-r3.1-r0/tf-a-stm32mp-v2.10.24-stm32mp-r3.1/../build/optee-sdcard-stm32mp257f-test2-mx/stm32mp2-stm32mp257f-test2-mx.o/opt/st/stm32mp2/5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sysroots/x86_64-ostl_sdk-linux/usr/libexec/aarch64-ostl-linux/gcc/aarch64-ostl-linux/13.4.0/ld: cannot find -lgcc: No such file or directory/opt/st/stm32mp2/5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10/sysroots/x86_64-ostl_sdk-linux/usr/libexec/aarch64-ostl-linux/gcc/aarch64-ostl-linux/13.4.0/ld: cannot find -lgcc_s: No such file or direc

Hi,I have a SoM based on STM32MP135c (QSMP-1351) and I try to enable the secure boot using STM32_Programmer_CLI (STM32CubeProgrammer v2.22.0)Here is the flash layout file used before updating OTP:#opt  Id   Name  Type  Device Offset Binary-    0x01  fsbl-boot    Binary none  0x0   tf-a-loader.stm32-    0x03  fip-boot    FIP   none  0x0   fip-loader.binI can write PKHTH without any issue:STM32_Programmer_CLI -c port=usb1 -otp write word=0x18 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x19 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1a value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1b value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1c value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1d value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1e value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1f value=0x????????When I want to lock device, I use the comm

We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.[Configuration under consideration]MPU：    STM32MP253FAK3Memory devices：    Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packagesBus width：    16-bit (Byte0 = device #1, Byte1 = device #2)Rank configuration：    Single rank (CS0 / CKE0 / ODT0 shared by the two devices)Total density：    2 GByte[Questions]1. Support for this topologyIs the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:16-bit interface: one x16 device connected point-to-point (Section 3.4)32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)We could not find any description of a configuration using x8 dev

Hello Experts,I am working on the STM32MP257F-EV1 board (MB1936 Var1.0 Rev.C-01) and following the official OpenSTDroid provisioning guide. I have successfully used flash-device(STM32CubeProgrammer v2.22.0 ) to flash the full eMMC starter image via DFU mode (FlashLayout_emmc_cm33tdcid.tsv). After that, I switched the boot mode from DFU to eMMC (M33-TD) and pressed USER2 + RESET to enter fastboot mode, as described in the documentation. However, instead of entering fastboot, the board goes into an infinite reboot loop.Observed behavior: Serial console (minicom) shows the following repeated sequence: iac exceptions: [159:128]=0x000001IAC exception ID: 128Ooops...[INF] System reset[INF] Reset reason: System reset (SYSRST) (0x94)[INF] init:pmic@33 STPMIC:20 V1.1[INF] welcome to MCUboot: TF-Mv2.1.3-4-g0a94de886[INF] cpu: STM32MP257FAI Rev.?[INF] board: stm32mp257f eval1[INF] board ID: MB1936 Var1.0 Rev.C-01[INF] dts: stm32mp257f-ev1-cm33tdcid-ostl-emmc-bl2.dts[INF] boot device: sdmmc2[INF]

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

Dear ST-Community,I was able to run QNX8 on stm32mp257f-dk (see it here: https://github.com/KozhinovAlexander/qnx8-bsp-stm32mp257f-dk)I have following boot-stage setup:#Opt Id Name Type IP Offset Binary- 0x01 fsbl-boot Binary none 0x0 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-programmer-usb.stm32- 0x02 fip-ddr FIP none 0x0 fip/fip-stm32mp257f-dk-ddr-opteemin-programmer-usb.bin- 0x03 fip-boot FIP none 0x0 fip/fip-stm32mp257f-dk-opteemin-programmer-usb.binP 0x04 fsbla1 Binary mmc0 0x00004400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32P 0x05 fsbla2 Binary mmc0 0x00044400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32PD 0x06 metadata1 FWU_MDATA mmc0 0x00084400 arm-trusted-firmware/metadata.binPD 0x07 metadata2 FWU_MDATA mmc0 0x000C4400 arm-trusted-firmware/metadata.binP 0x08 fip-a FIP mmc0 0x00104400 fip/fip-stm32mp257f-dk-opteemin-sdcard.binPED 0x09 fip-b FIP mmc0 0x00504400 nonePED 0x0A u-boot-env ENV mmc0 0x00904400 noneP 0x10 bootfs System mmc