STM32 MPUs Products and hardware related

I need the CPU to copy camera frames for tasks like screenshot-based recognition and uploading. However, in the data path (sensor → CSI → DCMIPP → DMA → DDR), the DMA mapping layer marks the memory as uncached, resulting in very slow speeds; the CPU read bandwidth is only ~143 MB/s—just one-eleventh of the speed of standard cached memory (1619 MB/s).Copying a 1280x960 image from DMA takes around 25ms, and the process becomes even slower at higher resolutions, leading to a poor user experience.Is there a way to make the DMA copy speed match that of standard cached memory (1619 MB/s)? 

Hello,I am a Master's student comparing FreeRTOS and Zephyr on the Cortex-M33 of the STM32MP257F-DK, with Linux running on the Cortex-A35. I measure task timing on the M33 with the DWT cycle counter and an oscilloscope, and I want a second core running a fixed bare-metal load in parallel to see how it affects the M33. A few things I could not find in the documentation:1. Cortex-M0+ as load generator. Can the M0+ run its own firmware at the same time as the M33 (and Linux on the A35)? Can it exchange data with the M33 (shared memory, mailbox, other), and which memories can it access? Who starts it?2. GPIOs for the M33. I need 2 or 3 pins that the M33 can toggle freely to measure with the oscilloscope. Which pins of the DK can be given to the M33, and what has to be changed (RIF, device tree)?3. Firmware already on the M33. Does the DK ship with any firmware running on the M33 (for example USB-PD, as I saw reported for the EV1)? Can I load my own firmware without breaking the board?4. Cy

EnvironmentBoard: ATK-DLMP257B (STM32MP257), ST official Yocto image (X-LINUX-TSNSWCH) Kernel 6.6.48 deptp 2.5.2 (Flexibilis DE-gPTP Edge daemon) Driver: edgx_pfm_lkm (TTTech EDGE Platform Host Interface Driver)GoalConfigure the on-board switch as an IEEE 802.1AS Peer-to-Peer Transparent Clock, so that forwarded Sync/Follow_Up frames carry the residence time in their correctionField.Configuration (factory default, unmodified) <Interface name="sw0p2"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Interface name="sw0p3"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Basic><one_step_clock>0</one_step_clock></Basic>deptp.service is active. deptp_tool --get-tc-port-dataset returns valid data (faulty false, peer-mean-path-delay ≈ 145 ns), while deptp_tool --get-port-dataset returns error rejected — confirming that deptp is actuall

​@Erwan SZYMANSKI, we are about to design a new hardware based on MP2.Is REV Y ETH1 port stable when used in RGMII mode?Is this config recommended?ETH1 in RGMII mode and ETH2 in RMII

Hello ST team and community,I am developing a custom STM32MP257-based MPU board and I want to create a customized Linux OS for our own product.I would like to understand the officially recommended approach and the limitations of using OpenSTLinux/Yocto versus an Ubuntu 24.04 ARM64 root filesystem.My target hardware is:MPU: STM32MP257F Custom PCB/SOM Cortex-A35 used for Linux Cortex-M33 may be used for real-time firmware Custom DDR/LPDDR4 configuration Custom Ethernet/USB/SD/eMMC/UART peripherals Custom Device Tree generated/configured using STM32CubeMX Development host: Ubuntu 24.04 LTSI understand that ST's current Distribution Package supports STM32MP25x and allows users to create their own Linux distribution. Thank You,Vijaya.

Hi ST Community,I’m looking for the schematic/reference design for B-LVDS7-WSVGA, or the LCD part number or datasheet of LCD used on this board.

Greetings,I have finished the schematics of my custom STM32MP13X based PCB, My aim with this PCB is to learn high speed digital circuit design & how the board bring up is done & various other things like loading RAM's timing information from an EEPROM to initialize RAM, etc.I would appreciate if my schematics could be reviewed & any potential issues could be pointed out before I start my PCB design (or worse, produce the PCBs) because I’m a student who’s funding this project from my part time job & I really don’t want to make an expensive mistake.The schematics are majorly based on STM32MP135-DK's reference schematics (MB1635) & I have attached the schematics (PDF) along with BoM file for package size information, etc.I would also like to mention that the schematics have been designed to keep costs low, This is also why most of the components will be sourced via LCSC & This is also why there’s no eMMC on-board. I also omitted the termination resistors on DDR bec

Hello ST Team,I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33? Is there any official resource ownership matrix available for STM32MP257F? Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33? Are there any peripherals that are exclusively accessible by one core and cannot be reassigned? How is ownership handled for the following peripherals? GPIO Ethernet MACs USB2.0 / USB3.0 FDCAN I2C SPI / OCTOSPI UART / USART SDMMC DDR Controller GPU / VPU / NPU LTDC / DSI / LVDS ADC / DAC Timers DMA / GPDMA Is there a document showing: Peripheral-to-core mapping Security attribution Trust

I’ve just recently started with the STM32 tool chain so some of these may be answered elsewhere. Platform is Debian.Some problems have been encountered due to the editor in STM Cube IDE doing unexpected things, one of which led to the loss of a considerable amount of code. In general the editor is a bit week compared with e.g. Sublime text   Your IDE designers should try that - when copying and pasting, the indentations are correct, with CUBE the text ends up over indented. I’m now editing in Sublime and then pasting the complete text into Cube.ST-link problem: This has a uart channel, on my STM32F4 Nucleo board, this is prewired to UART3 of the target, for printf type debugging. However, there is limited documentation on connecting a terminal to this UART (ST-Link PC end), and the listings in the /dev folder are :The debian terminal program “screen” will not connect to any of these. Also, on the redirection of printf on the target: most of the on-line resources for this topic indicate

Hi,I try to follow the instruction from this link to compile the “device-tree” again. First of all, the 3 primary components (FLASH- SOURCE- and SDK-x86 ...) are extracted under the WORKDIR, together with MyDeviceTree generated from the STMCubeMX. Next, the dedicated variables EXTDT_DIR, FWDDR_DIR, FIP_DEPLOYDIR_ROOT are set-up.I did also run the SDK environment to prepare for the next steps.Regarding “unpack and patch sources”, I follow the instruction line by line and did successfully.Then for the “regenerate the kernel DTB”, I got stuck at the line “make” the “.dtb” files. For this line, I changed the command as follow:MY_DEMO → MP15 (which is my project name) /linux → /kernel (since I couldn’t find the sub-dir “linux” in the DeviceTree directory) stm32mp135f → stm32mp157d -my_demo- → mp15→ Hence the file stm32mp135f-my_demo-mx.dtb will become stm32mp157d-mp15-mx.dtb, which matched with the stm32mp157d-mp15-mx.dts from the ../kernel directory.However I got the following errors and d

Hello,According to Table 56 (Output voltage characteristics for all I/Os) in the STM32MP213FAL datasheet, the maximum VOL is specified as 0.4V under high load conditions (IOL = 5.5mA to 20mA).In my application, the connected device has a strict VIL(Min) requirement of 0.35V. My actual load current is very low, around 10uA.While I understand that VOL should stay very close to 0V under such a low load due to the CMOS structure, the datasheet only provides the Max 0.4V limit.Strictly speaking, this does not show a match with my 0.35V requirement on paper.Could you provide any reference curves, typical characteristics, or internal RON (on-resistance) values for the I/O pins to confirm that VOL drops well below 0.35V under a 10uA load? Thank you in advance for your support. 

Evaluation of Display GRAM FunctionalityThe STM32MP157F-DK2 development board is equipped with an OTM8009A display.Link:Display panels hardware components - stm32mpuThis IC includes GRAM storage, which theoretically supports maintaining the display output even after the MPU enters sleep mode.Are there any available test results or evaluation conclusions regarding this?

According to the STM32MP257 datasheet:"1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY" "1× PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)"I would like to clarify:Can the USB3DR peripheral be used as a USB 3.0 SuperSpeed port while simultaneously supporting USB 2.0 High-Speed operation on the same connector? Is the embedded USB 2.0 PHY always available when the USB3DR interface is enabled? When PCIe is not used, can the USB3DR interface provide both the 480 Mbit/s USB 2.0 and 5 Gbit/s USB 3.0 links together as a standard USB 3.x port? Is the PHY sharing limitation only between PCIe and USB 3.0 SuperSpeed, or does it also affect USB 2.0 functionality?Any clarification on the USB/PCIe PHY sharing architecture would be appreciated.

Hello ST team,I noticed what appears to be a documentation typo in the STM32MPU Wiki page “How to configure TSN switch”, section 3.1 – Run the PTP stack.The documentation states:“dePTP stack is started by default. To start it using via systemctl:”but the command shown immediately after that sentence is:systemctl stop deptpI believe the intended command is:systemctl start deptpThis is also consistent with the later “How to trace the PTP stack” section of the same page, where the documentation correctly uses:systemctl stop deptpto stop the service, and:systemctl start deptpto start it again.The Qbv section also states that gPTP synchronization should be started beforehand and thatdeptpis started by default.Could you please confirm and correct the command in section 3.1 if this is indeed a documentation typo?Thank you.

Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23? Is this specified in any documentation?

Hello Team,We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:Will this impact DDR functionality, signal integrity, or overall system reliability? Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?Your confirmation and guidance will help us proceed with confidence before finalizing the board design.DDR Routing imageMeasuring toolLayer Stack-up 

We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.[Configuration under consideration]MPU：    STM32MP253FAK3Memory devices：    Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packagesBus width：    16-bit (Byte0 = device #1, Byte1 = device #2)Rank configuration：    Single rank (CS0 / CKE0 / ODT0 shared by the two devices)Total density：    2 GByte[Questions]1. Support for this topologyIs the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:16-bit interface: one x16 device connected point-to-point (Section 3.4)32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)We could not find any description of a configuration using x8 dev

Hello Experts,I am working on the STM32MP257F-EV1 board (MB1936 Var1.0 Rev.C-01) and following the official OpenSTDroid provisioning guide. I have successfully used flash-device(STM32CubeProgrammer v2.22.0 ) to flash the full eMMC starter image via DFU mode (FlashLayout_emmc_cm33tdcid.tsv). After that, I switched the boot mode from DFU to eMMC (M33-TD) and pressed USER2 + RESET to enter fastboot mode, as described in the documentation. However, instead of entering fastboot, the board goes into an infinite reboot loop.Observed behavior: Serial console (minicom) shows the following repeated sequence: iac exceptions: [159:128]=0x000001IAC exception ID: 128Ooops...[INF] System reset[INF] Reset reason: System reset (SYSRST) (0x94)[INF] init:pmic@33 STPMIC:20 V1.1[INF] welcome to MCUboot: TF-Mv2.1.3-4-g0a94de886[INF] cpu: STM32MP257FAI Rev.?[INF] board: stm32mp257f eval1[INF] board ID: MB1936 Var1.0 Rev.C-01[INF] dts: stm32mp257f-ev1-cm33tdcid-ostl-emmc-bl2.dts[INF] boot device: sdmmc2[INF]

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

Hello,We are designing a custom board using the STM32MP157FAC1 device (361 balls with 0.5 mm pitch).As per AN5031 (Page 50), laser vias with a 100 µm (~4 mil) drill hole diameter and 250 µm (~10 mil) outer pad diameter are recommended for BGA balls located within the 0.5 mm pitch matrix. A snapshot of the relevant section is attached for the reference.We would like to clarify whether a Via-On-Pad strategy can be used instead of laser vias for the BGA balls within the 0.5 mm pitch matrix of STM32MP157FAC1 device.Specifically, can we use a via of 200 µm (~8 mil) drill hole diameter and 400 µm (~16 mil) outer pad diameter as via-on-pad on the STM32MP157FAC1 BGA pads instead of the recommended laser vias ? Kindly confirm whether this approach is acceptable from the CAD layout perspective and whether it can be used in the CAD layout of our design.Regards,PS  

Hello everyone,When using libcamera on the STM32MP257 platform (ATK-DLMP257B development board with IMX335 sensor), the DCMIPP driver fails to queue stats buffers to /dev/video4, returning -EINVAL. This causes libcamera to crash with an assertion failure during stream shutdown.Additionally, the DCMIPP post-processor (dcmipp_main_postproc) refuses all YUV format configurations (NV12, YU12, YUV420, etc.), returning Invalid argument (22) for each attempt. The hardware only accepts RGB888/RGB565 output formats.When using libcamera on STM32MP257 platform with IMX335 sensor, the DCMIPP driver fails to queue stats buffers to `/dev/video4`, returning `-EINVAL`. This causes libcamera to crash with an assertion failure (`cache_->isEmpty()`) during stream shutdown.Linux kernel version is 6.6.48.libcamera version is v0.3.0+dirty.Steps to ReproduceBasic libcamera capture with fakesinkgst-launch-1.0 -v libcamerasrc ! \ video/x-raw,format=NV12,width=1920,height=1080,framerate=30/1 ! \ fakesi

I am writing this to help.I have just received my EVB STM32MP257F-DK.When I have connected my USB cable in "USB PWR STLNK".LD5 and LD6 were RED,  LD11 was flashing GREEN once.Installed the SD card and nothing, no boot ?Win11 was claiming that the driver is fine and the latest.The USB port were displayed as regular: USB PORT COM9 and COM10.Pressing the RESET button B1 nothing: No BOOT, no bad character on both ports ???Disconnecting the USB cable was well detected by Tera Term but nothing else.I have decided to install STM32CubeProgrammer Winn64 to check ithe ST-LINK by trying to connect.During the installation of the tool, the installer has advised  that it is installing a driver.With no intervention, my EVB started to work, booting LINUX and all the LEDS have started flashing like a chritmasResetting the EVB, we can see Linux booting on  port COM10 115200,8,N1See the image attached when the driver work fine and how it is displayed in Win11 device manager.Have fun.Best regards,SuperGDx

Hello ST team.I am working on the boot chain from qspi NAND flash memory. The board is based on the STM32MP135F SOC and the w25n01gvzeig winbond 128MB IC. The IC is sitting on qspi bank 1 on the default BOOTROM pins (AN5474 p49).I have already succeeded the bootchain for EMMC and USB uboot successfully locates and flashes the nand with the partitions I have specified. But as set the boot pins to 111 I get 0 logs from the serial.By reading in the forum I suspect that the OTP should be programmed with the NAND layout configuration but I would like to be sure. Note the I have build tf-a with the STM32_SPI_NAND=1 on the extra flags and I get a boot log from NAND boot if i perform software reset from uboot usb.With softreset and tfa hardcoded the otp value for nand block nb[7:0]:STM32MP> resetresetting ...▒NOTICE: CPU: STM32MP135F Rev.YNOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11INFO: Reset reason (0x74):INFO: System

Dear ST Support Team,I am an embedded systems engineer currently designing a custom PCB around the STM32MP257F microprocessor for a product application (a camera-based embedded system). I am using the STM32MP257F-EV1 evaluation board as our reference design for both hardware and software bring-up.We are now finalizing our own DDR memory design and are running into difficulty sourcing a DDR part that is confirmed compatible with the STM32MP257F. We understand the EV1 reference design uses two 16-Gbit DDR4 DRAMs (16-bit wide, populated for a 32-bit total bus), and that the STM32MP257 DDR controller supports DDR3L up to 2133, DDR4 up to 2400, and LPDDR4 up to 2400, in 16-bit or 32-bit configurations. However, when we check current market availability, we are not able to find DDR parts that are clearly qualified or validated against the STM32MP257F DDR controller, and we want to avoid selecting a part that causes signal integrity, timing, or DDR-training issues on our own layout.Could you

The MB1854B camera on the STM32MP257FDK fails to open; clicking the camera icon on the desktop results in a white screen. Is this related to hot-plugging the camera? How can this be resolved? dmesg -w log:stm32-csi 48020000.csi: Timeout waiting for VC0 stopstm32-csi 48020000.csi: Failed to stop stream:0