STM32 MPUs Products and hardware related

 # STM32MP257F-DK: USB3DR in peripheral (device) mode only links at High-Speed Report prepared for submission to STMicroelectronics (ST Community / support). ## 1. Summary On an STM32MP257F-DK running the official ST OpenSTLinux image, the Type-C port (USB3DR + COMBOPHY)enumerates SuperSpeed (5 Gbps) devices correctly when the board is **host**. When the same board is**peripheral (gadget)**, the link always trains to **High-Speed (480 Mbps)** and never to SuperSpeed.This happens against a PC USB 3.0 port and against a second identical DK, with both Type-C plugorientations, and with a cable verified to carry SuperSpeed lines. Device tree, COMBOPHY and DWC3 glue configuration follow the ST wiki exactly, and the M33`USBPD_DRP_UCSI` firmware logs show the USB3 switch (PH2/PH3) being driven for both orientations. **Question for ST:** is SuperSpeed in peripheral mode supported on the STM32MP257F-DK Type-C port with thestock `USBPD_DRP_UCSI` firmware? If yes, what is missing in our setup? ##

Hi,In this earlier discussion, virtualization was described as unsupported on STM32MP25, but the datasheet lists hardware virtualization support.Does this mean ST does not provide supported hypervisor software, or are there hardware/firmware restrictions? Would it be possible to port the open-source Bao hypervisor to the STM32MP257F-DK?Thank you.

Hello,I would design a PCB a compatible with both STM32MP23x and STM32MP25x series, using VFBGA424 package.I would support both 16x and 32x DDR4 controller configuration, so I will use fly-by routing to avoid stubs. STM => DDR4A => DDR4B => termination The question is:in the case we use 16x configuration, it is better to have the only memory chip near o far with respect to the STM32?I mean, the only populated chip shall be DDR4A or DDR4B? ThanksAndrea 

Link https://www.st.com/resource/en/ibis_model/stm32mp2-ibis.zipThere should be STM32MP211_213_215  

Hello,According to Table 56 (Output voltage characteristics for all I/Os) in the STM32MP213FAL datasheet, the maximum VOL is specified as 0.4V under high load conditions (IOL = 5.5mA to 20mA).In my application, the connected device has a strict VIL(Min) requirement of 0.35V. My actual load current is very low, around 10uA.While I understand that VOL should stay very close to 0V under such a low load due to the CMOS structure, the datasheet only provides the Max 0.4V limit.Strictly speaking, this does not show a match with my 0.35V requirement on paper.Could you provide any reference curves, typical characteristics, or internal RON (on-resistance) values for the I/O pins to confirm that VOL drops well below 0.35V under a 10uA load? Thank you in advance for your support. 

Hi there I have a STM32MP257f-DK board running the latest Linux, and I’m trying to output to a waveshare 9.3” HDMI display at its native resolution. 1600x600I can output to it at 1920x1080. and I can output to the display from my Mac at it’s native 1600x600. I see a slight flicker when I try send video then black. then the display goes to sleep. So the display is losing sync.linux reports the output is working, but it seems it’s something to do with the ADZ7xx chip.any ideas?

Dear ST Support Team,I am working with the STM32MP257F-EV1 evaluation board and have found an issue with some of the on-board crystals while checking their clock frequencies.Observations:- X1: no frequency is observed- X2: no frequency is observed- X7 (ST-LINK crystal): a correct frequency of 24 MHz is observed againCould you please help me with the following:1. Possible reasons why X1 and X2 are not oscillating on this board.2. Any recommended checks (supply, load capacitors, bias, probing method) to confirm whether this is a hardware fault or a measurement issue.3. Whether this could be a defective board, and if so, the process for replacement or repair.I can share measurement screenshots, photos of the board, and further details if needed.Thank you for your support. I look forward to your reply.Best regards,Radha 

I need the CPU to copy camera frames for tasks like screenshot-based recognition and uploading. However, in the data path (sensor → CSI → DCMIPP → DMA → DDR), the DMA mapping layer marks the memory as uncached, resulting in very slow speeds; the CPU read bandwidth is only ~143 MB/s—just one-eleventh of the speed of standard cached memory (1619 MB/s).Copying a 1280x960 image from DMA takes around 25ms, and the process becomes even slower at higher resolutions, leading to a poor user experience.Is there a way to make the DMA copy speed match that of standard cached memory (1619 MB/s)? 

Hello,I am a Master's student comparing FreeRTOS and Zephyr on the Cortex-M33 of the STM32MP257F-DK, with Linux running on the Cortex-A35. I measure task timing on the M33 with the DWT cycle counter and an oscilloscope, and I want a second core running a fixed bare-metal load in parallel to see how it affects the M33. A few things I could not find in the documentation:1. Cortex-M0+ as load generator. Can the M0+ run its own firmware at the same time as the M33 (and Linux on the A35)? Can it exchange data with the M33 (shared memory, mailbox, other), and which memories can it access? Who starts it?2. GPIOs for the M33. I need 2 or 3 pins that the M33 can toggle freely to measure with the oscilloscope. Which pins of the DK can be given to the M33, and what has to be changed (RIF, device tree)?3. Firmware already on the M33. Does the DK ship with any firmware running on the M33 (for example USB-PD, as I saw reported for the EV1)? Can I load my own firmware without breaking the board?4. Cy

EnvironmentBoard: ATK-DLMP257B (STM32MP257), ST official Yocto image (X-LINUX-TSNSWCH) Kernel 6.6.48 deptp 2.5.2 (Flexibilis DE-gPTP Edge daemon) Driver: edgx_pfm_lkm (TTTech EDGE Platform Host Interface Driver)GoalConfigure the on-board switch as an IEEE 802.1AS Peer-to-Peer Transparent Clock, so that forwarded Sync/Follow_Up frames carry the residence time in their correctionField.Configuration (factory default, unmodified) <Interface name="sw0p2"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Interface name="sw0p3"><profile>gptp</profile><mode>tc</mode><delay>p2p</delay></Interface><Basic><one_step_clock>0</one_step_clock></Basic>deptp.service is active. deptp_tool --get-tc-port-dataset returns valid data (faulty false, peer-mean-path-delay ≈ 145 ns), while deptp_tool --get-port-dataset returns error rejected — confirming that deptp is actuall

​@Erwan SZYMANSKI, we are about to design a new hardware based on MP2.Is REV Y ETH1 port stable when used in RGMII mode?Is this config recommended?ETH1 in RGMII mode and ETH2 in RMII

Hello ST team and community,I am developing a custom STM32MP257-based MPU board and I want to create a customized Linux OS for our own product.I would like to understand the officially recommended approach and the limitations of using OpenSTLinux/Yocto versus an Ubuntu 24.04 ARM64 root filesystem.My target hardware is:MPU: STM32MP257F Custom PCB/SOM Cortex-A35 used for Linux Cortex-M33 may be used for real-time firmware Custom DDR/LPDDR4 configuration Custom Ethernet/USB/SD/eMMC/UART peripherals Custom Device Tree generated/configured using STM32CubeMX Development host: Ubuntu 24.04 LTSI understand that ST's current Distribution Package supports STM32MP25x and allows users to create their own Linux distribution. Thank You,Vijaya.

Hi everyone,I’m developing an open-source project called Embedded Power Audit, a lightweight shell-based tool for inspecting power-management and thermal information on embedded Linux devices.The project has already been tested on several platforms, including: NXP i.MX6 NXP i.MX8M Plus NXP i.MX93 Raspberry Pi AMD/Xilinx Zynq I would now like to add support for STM32MP25.If anyone here has access to an STM32MP25-based board running OpenSTLinux, Yocto, or another embedded Linux distribution, I would really appreciate a very simple test:run the script and share the generated output with me.The tool is read-only and mainly inspects Linux interfaces such as: CPU frequencies and governors cpuidle states thermal zones memory information interrupts device runtime power-management settings other power-related sysfs/procfs interfaces Repository:https://github.com/br1pastore/Embedded-Power-AuditAt this stage I’m mainly interested in understanding which power-management interfa

Hi ST Community,I’m looking for the schematic/reference design for B-LVDS7-WSVGA, or the LCD part number or datasheet of LCD used on this board.

Greetings,I have finished the schematics of my custom STM32MP13X based PCB, My aim with this PCB is to learn high speed digital circuit design & how the board bring up is done & various other things like loading RAM's timing information from an EEPROM to initialize RAM, etc.I would appreciate if my schematics could be reviewed & any potential issues could be pointed out before I start my PCB design (or worse, produce the PCBs) because I’m a student who’s funding this project from my part time job & I really don’t want to make an expensive mistake.The schematics are majorly based on STM32MP135-DK's reference schematics (MB1635) & I have attached the schematics (PDF) along with BoM file for package size information, etc.I would also like to mention that the schematics have been designed to keep costs low, This is also why most of the components will be sourced via LCSC & This is also why there’s no eMMC on-board. I also omitted the termination resistors on DDR bec

Hello ST Team,I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33? Is there any official resource ownership matrix available for STM32MP257F? Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33? Are there any peripherals that are exclusively accessible by one core and cannot be reassigned? How is ownership handled for the following peripherals? GPIO Ethernet MACs USB2.0 / USB3.0 FDCAN I2C SPI / OCTOSPI UART / USART SDMMC DDR Controller GPU / VPU / NPU LTDC / DSI / LVDS ADC / DAC Timers DMA / GPDMA Is there a document showing: Peripheral-to-core mapping Security attribution Trust

Hi,I try to follow the instruction from this link to compile the “device-tree” again. First of all, the 3 primary components (FLASH- SOURCE- and SDK-x86 ...) are extracted under the WORKDIR, together with MyDeviceTree generated from the STMCubeMX. Next, the dedicated variables EXTDT_DIR, FWDDR_DIR, FIP_DEPLOYDIR_ROOT are set-up.I did also run the SDK environment to prepare for the next steps.Regarding “unpack and patch sources”, I follow the instruction line by line and did successfully.Then for the “regenerate the kernel DTB”, I got stuck at the line “make” the “.dtb” files. For this line, I changed the command as follow:MY_DEMO → MP15 (which is my project name) /linux → /kernel (since I couldn’t find the sub-dir “linux” in the DeviceTree directory) stm32mp135f → stm32mp157d -my_demo- → mp15→ Hence the file stm32mp135f-my_demo-mx.dtb will become stm32mp157d-mp15-mx.dtb, which matched with the stm32mp157d-mp15-mx.dts from the ../kernel directory.However I got the following errors and d

Evaluation of Display GRAM FunctionalityThe STM32MP157F-DK2 development board is equipped with an OTM8009A display.Link:Display panels hardware components - stm32mpuThis IC includes GRAM storage, which theoretically supports maintaining the display output even after the MPU enters sleep mode.Are there any available test results or evaluation conclusions regarding this?

According to the STM32MP257 datasheet:"1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY" "1× PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)"I would like to clarify:Can the USB3DR peripheral be used as a USB 3.0 SuperSpeed port while simultaneously supporting USB 2.0 High-Speed operation on the same connector? Is the embedded USB 2.0 PHY always available when the USB3DR interface is enabled? When PCIe is not used, can the USB3DR interface provide both the 480 Mbit/s USB 2.0 and 5 Gbit/s USB 3.0 links together as a standard USB 3.x port? Is the PHY sharing limitation only between PCIe and USB 3.0 SuperSpeed, or does it also affect USB 2.0 functionality?Any clarification on the USB/PCIe PHY sharing architecture would be appreciated.

Hello ST team,I noticed what appears to be a documentation typo in the STM32MPU Wiki page “How to configure TSN switch”, section 3.1 – Run the PTP stack.The documentation states:“dePTP stack is started by default. To start it using via systemctl:”but the command shown immediately after that sentence is:systemctl stop deptpI believe the intended command is:systemctl start deptpThis is also consistent with the later “How to trace the PTP stack” section of the same page, where the documentation correctly uses:systemctl stop deptpto stop the service, and:systemctl start deptpto start it again.The Qbv section also states that gPTP synchronization should be started beforehand and thatdeptpis started by default.Could you please confirm and correct the command in section 3.1 if this is indeed a documentation typo?Thank you.

Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23? Is this specified in any documentation?

Hello Team,We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:Will this impact DDR functionality, signal integrity, or overall system reliability? Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?Your confirmation and guidance will help us proceed with confidence before finalizing the board design.DDR Routing imageMeasuring toolLayer Stack-up 

We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.[Configuration under consideration]MPU：    STM32MP253FAK3Memory devices：    Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packagesBus width：    16-bit (Byte0 = device #1, Byte1 = device #2)Rank configuration：    Single rank (CS0 / CKE0 / ODT0 shared by the two devices)Total density：    2 GByte[Questions]1. Support for this topologyIs the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:16-bit interface: one x16 device connected point-to-point (Section 3.4)32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)We could not find any description of a configuration using x8 dev

Hello Experts,I am working on the STM32MP257F-EV1 board (MB1936 Var1.0 Rev.C-01) and following the official OpenSTDroid provisioning guide. I have successfully used flash-device(STM32CubeProgrammer v2.22.0 ) to flash the full eMMC starter image via DFU mode (FlashLayout_emmc_cm33tdcid.tsv). After that, I switched the boot mode from DFU to eMMC (M33-TD) and pressed USER2 + RESET to enter fastboot mode, as described in the documentation. However, instead of entering fastboot, the board goes into an infinite reboot loop.Observed behavior: Serial console (minicom) shows the following repeated sequence: iac exceptions: [159:128]=0x000001IAC exception ID: 128Ooops...[INF] System reset[INF] Reset reason: System reset (SYSRST) (0x94)[INF] init:pmic@33 STPMIC:20 V1.1[INF] welcome to MCUboot: TF-Mv2.1.3-4-g0a94de886[INF] cpu: STM32MP257FAI Rev.?[INF] board: stm32mp257f eval1[INF] board ID: MB1936 Var1.0 Rev.C-01[INF] dts: stm32mp257f-ev1-cm33tdcid-ostl-emmc-bl2.dts[INF] boot device: sdmmc2[INF]

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download