STM32 MCUs Embedded software

STM32N6: Black screen after HAL_NVIC_SystemReset() — FSBL not booting, works fine after NRST/power cycleGövde:Hello,I have a bootloader (FSBL) and a separate application on anSTM32N645L0, running from external XSPI NOR flash MX25UM25645GXDI00 in memory-mapped XIP mode (Octal DTR).Setup:FSBL configures the external flash into Octal DTR mode (volatile CR) at every boot and shows update/bootloader graphics on the display The application runs its own graphics To enter bootloader mode from the application, call HAL_NVIC_SystemReset()Problem:After HAL_NVIC_SystemReset(), the device stays on a black screen — the FSBL graphics never appear. However, if I reset via the NRST button or a full power cycle, everything boots normally.What I suspect:Since the N6 is flashless, BootROM must read the FSBL from external flash in standard SPI mode. My theory is that after a software reset the flash chip stays in Octal DTR mode (it doesn't lose power), so BootROM cannot read the FSBL at all.Questions:Is th

Hello everyone,I'm trying to configure the SAI and GPDMA peripherals on an STM32 to acquire audio from an I2S microphone. My goal is to capture a 32-bit, 2-channel audio stream at a 16 kHz sample rate, with the STM32 acting as the clock master. I've followed the steps below, but I'm running into two main issues:While the HAL_SAI_RxCpltCallback and HAL_SAI_RxHalfCpltCallback functions are being called, the acquisition buffer remains unchanged (full of zeros).I'm seeing a 16 kHz signal on all three I2S lines (SCK, FS, and SD), which is incorrect. The clock (SCK) should be much higher.Here's a summary of the steps I've taken:PLL4 Configuration: I've configured PLL4 to generate a 1.024 MHz clock (16 kHz * 64 = 1.024 MHz). This clock feeds into the IC7 peripheral.GPDMA1 Configuration: I've enabled the clock and interrupts for GPDMA1 Channel 0 and added a linked-list initialization.SAI1 Block B1 Configuration: I've set up the SAI handle for I2S standard, 32-bit data, 16 kHz audio frequency,

Hi.I’m using CubeIDE, CubeMX and HAL to create an application for an STM32L451.I’ve setup USART1 to receive via DMA in circular mode and detect line idle, starting receptions with HAL_UARTEx_ReceiveToIdle_DMA(), and processing receptions in callback HAL_UARTEx_RxEventCallback().All seems to work fine except that the TC (transfer complete, or full buffer) interrupt never happens.HT (half transfer, or half of the buffer reached) and line idle do interrupt.I’m providing HAL_UARTEx_ReceiveToIdle_DMA() a buffer of size 128 bytes. I’m logging the value of the size argument to HAL_UARTEx_RxEventCallback(). When I manually send a message of 20 bytes repeatedly, but slowly enough to ensure line idle triggers, the callback is called with the following size values: 20, 40, 60, 64, 80, 100, 120, 120, 12, 32, 52, 64, 72, 92, 112, 112, 4, 24, (etc).You can see that line idle works, and also that HT is issued in the middle of a reception (size == 64), but TC isn’t, there’s no size equal to 128.What’s

Hi, I am developing an I3C target application that responds to I3C private messages from the controller. The application starts by registering the Tx callback.static void I3C_TxCompleteCallback(hal_i3c_handle_t *hi3c); // The callback is registered during initialization hal_status_t status = HAL_I3C_TGT_RegisterTxCpltCallback(hI3C, I3C_TxCompleteCallback); if (status != HAL_OK) { SWD_printf("HAL_I3C_TGT_RegisterTxCpltCallback failed.\n"); return status; }The target responds to the controller: hal_status_t status; hal_i3c_handle_t *hI3C = mx_i3c1_gethandle(); status = HAL_I3C_TGT_Transmit_IT(hI3C, I3C_TxBuffer, 8); if (status != HAL_OK) { SWD_printf("HAL_I3C_TGT_Transmit_IT: %lx\n", status); return status; }The controller receives 8 bytes of data and the data is correct but the TxComplete callback does not trigger on the target side.I placed a breakpoint inside the HAL I3C_Tgt_ISR show below./** * @brief Interrupt Sub-Routine which han

Dear STM32 Advisor,   I'll design a system based on Nucleo 64 H533RE. The system will act as USB CDC and USB HID Keyboard at the same time. The idea is when the CDC receive a character, here for example "F" then the Nucleo H533RE will output a high going pulse. And, if the Nucleo H533RE receive falling pulse external interrupt, the the Nucleo H533RE will press the F8 key. As a beginner on STM32, is it possible?   Thanks and regards,   Fuad Purnomo.

Hello,I have a project that uses I3C to connect a Nucleo-C562RE with an STM32C542CCT6 MCU. The setup was working fine with HAL 2.0.0 but it does not work in 2.1.0. I generated the code with MX2 and I observed that it is identical to the code in the private_it_controller example code. I stepped through the mx_i3c1_init function and I noticed that the moment the GPIO for SDA and SCL are enabled, the I3C clock (SCL) is turned on (visible on the oscilloscope) and does not stop. I don’t see how this could be correct. When I try to start DAA it fails instantly (the error callback is invoked) and the SDA line never changes state (it stays HIGH after reset).Can someone help with this issue?Thank you,Gil

Hello ST Community,We are working with the STM32N657X0H3Q controller and interfacing an S80KS5123GABHB020 HyperRAM using the XSPI1 (Octal SPI) interface. The external HyperRAM is intended to be used as the LTDC frame buffer.We have configured the HyperRAM in memory-mapped mode, and according to our configuration, it should be accessible at the address 0x90000000.However, we are unable to access this memory region. Any read or write operation to 0x90000000 fails. For initial testing, we have configured the XSPI clock to 2 MHz.Our setup is based on the STM32N657-DK board example, and we have followed the same memory-mapped configuration.Could you please let us know if any additional configuration is required to access the HyperRAM at 0x90000000? Specifically, we would like to know:Are there any additional XSPI configurations required for memory-mapped mode? Does the MPU or cache need to be configured for this external memory region? Are there any system, clock, or pin configurations that

I am working with an STM32H743VIT6 and I am trying to migrate an existing bare-metal LVGL + SDMMC + FatFs project to FreeRTOS + LVGL + SDMMC + FatFsIn my previous bare-metal project, the SD card worked correctly.However, after creating a new project using STM32CubeMX with FreeRTOS + SDMMC + FatFs, the FatFs mount operation fails from the beginning.The problem occurs when calling:f_mount(&SDFatFS, SDPath, 1);void LVGL_Task(void *argument) { (void)argument; printf("LVGL Task START\r\n"); FRESULT fres; printf("before f_mount\r\n"); fres = f_mount(&SDFatFS, (TCHAR const *)SDPath, 1); printf("after f_mount, result = %d\r\n", fres); if (fres == FR_OK) { printf("SD success\r\n"); } else { printf("SD fail\r\n"); } printf("before ui_init\r\n"); ui_init(); printf("after ui_init\r\n"); while (1) { uint32_t delay = lv_timer_handler(); if (delay > 1000) delay = 10; osDelay(delay); }} I have placed the buf address in AXI SRAM and confirmed that the addres

Hello,I am using an NUCLEO-N657X0-Q (STM32N657) and developing an application using the FSBL + XIP application structure. Development EnvironmentSTM32CubeIDE: 2.2.0 STM32CubeMX: 6.18.1 STM32CubeProgrammer: 2.22.0 The application is stored in external Flash and executed in XIP mode. I can successfully program the external Flash and enter/run the Appli project through the debugger.The application works normally as long as I do not enable the timer update interrupt.However, when I enable a TIM update interrupt in the Appli project, the application stops working when the interrupt occurs.My project structure is:FSBL └─ Initializes the external Flash and starts the XIP applicationAppli └─ Executed from external Flash └─ TIM update interrupt enabled hereThe timer itself is initialized in the Appli project.The interrupt handler is also located in the Appli project's stm32n6xx_it.c:extern TIM_HandleTypeDef htim1;void TIM1_UP_IRQHandler(void){ HAL_TIM_IRQHandler(&htim1);}and the call

Hello,We are developing a battery-operated GPS asset tracker. To conserve power, the STM32 enters STOP mode every 10 minutes and wakes up via RTC alarm to fetch the current location.Problem:After waking up from STOP mode and toggling the power/enable pin of the GPS module, the GNSS chip takes over 60–90 seconds to re-acquire a 3D fix (Cold Start), which drains the battery significantly. Even when backup power (VBACKUP pin) is maintained to save ephemeris data, warm start is not triggering reliably.Setup:MCU: STM32L4 Low-Power seriesPower Management: WFI / STOP 2 modeIs there a best practice for managing GPIO states and UART lines before entering STOP mode to prevent current leakage into the GPS module's RX/TX pins?Best regards.

When calling HAL_QSPI_Abort() to disable memory mapped mode, with the memmap timeout active, I find that there is a race condition that can cause the abort to fail when it should not. If the memmap timeout happens after the abort function's check of the busy flag, but before it can write to the abort bit, the TC flag will never be set and the abort function will wait for the configured qspi timeout, then return an error.I am testing this on a STM32F769I-DISCO board.I have found that the following patch will fix the issue: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 8404466..01a06ca 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -2381,19 +2381,19 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABOR

I have seen a few other posts about ADC2 calibration issues without resolution.  I’m creating this new post to provide a resolution.Using ADC1 and ADC2 in Dual mode on STM32H745 from CM4 running at 240 MHz.  10% of boards in production (20/200) were continuously watchdog resetting.  This was traced to the ADC2 calibration getting stuck in a loop for 5 minutes (and hardware watchdog of 4s would trip).  At 240 MHz, this timeout loop should only be 2.4s.  (It would be better to use a timer function, but this is STM ADC HAL code) /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)I’m not sure what is going on in the H7 silicon that makes the status register read so slow or why it isn’t changing in the expected 2.4s max, but STM provided a work-around.  Change the order of initialization to remove the Dual Mode config from the .ioc - generated code in ma

HelloI have my own board with STM32G071KBT6 microcontroller. I successfully comunicate with charger by PD protocol and I receive up to 21 V (PPS). But I need above 21V. I have power bank with AVS up to 28V and USB cable with e-marker (up to 240W). How to configure the stack to receive EPR parameters? I have no TCPP IC, but I use my own protection circuit. In the trace the EPR commands isn't present. I use STM32CubeIDE 2.1.1 and STM32CubeMX 6.17.0.Thanks a lot and best regards

Hello,is there a definitive application note to interface PDM mics with MDF/ADF?there is AN5027 but it doesn’t tell about MDF or ADF. If I insert correctly MDF/ADF is a newer version of DFSDM but I would like if someone can point me to the interfacing wet stm32cubeMX for MDF/ADF usage with PDM mics showing  configurations to interface N number of MICs(1-8) for a required sampling rate(16-96 KHz) if possible?which one to choose MDF or ADF?or both are same?Thanks a lot in advance !regards,S 

We have a current application in which our F7 is connected to an external Microchip PHY which provides a 50 MHz reference clock for RMII.  We are attempting to place the system into a low power mode in which we disable the PHY thus stopping the reference clock.  Is there a way to do this that will not cause the network stack on the MCU to fail?  We are using Zephyr as our RTOS which may or may not be relevant.

Hi all - I have a problem getting DMA working with SPI, for communication with an MCP3564R ADC as one task in a complex project running on FreeRTOS. I have made a stripped-down version of the project that just does the ADC reading task. It runs on a bare Nucleo board and illustrates the basic problem which shows up from the first transmit, so a connected ADC isn’t needed to see the problem.The code uses SPI3 at 20MHz (although the problem occurs at lower speeds as well)The GPIO pins I’m using are not the defaults:GPDMA1 is configured with two channels for SPI3 TX and RX:My code can be configured to use the HAL SPI DMA APIs or the interrupt APIs like so:static uint8_t write_register(const uint8_t * reg_write_cmd_p, uint8_t num_bytes){ HAL_StatusTypeDef hal_status; BaseType_t wait_ret_val; uint32_t notify_bits; uint8_t ret_val = 0; /* Failure */#if (MCP3564_HAL_SPI_MODE == MCP3564_USE_HAL_SPI_DMA_MODE) hal_status = HAL_SPI_Transmit_DMA(&ADC_SPI_PERIPH_HANDLE, reg_write

hi I am trying to get an sd card to work with my custom board, uses STM32F412RET6.when i try to mount or do anything other than init in 1 bit mode the code gets stuck at this point. I have been able to read block size and number from the SD card but that is it. while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT)) { if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) { *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); index++; } else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT)) { break; } if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } 

Hello ST Community,am working with a Nucleo-H753ZI board where the STM32H753ZI is configured as an SPI1 slave, and the SPI master is a TI AM64x R5F core.The goal is for the STM32 to continuously transmit 4-byte frames over SPI (using DMA) whenever the master clocks the bus.However, the problem is:The master is receives only FF FF/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes --------------

Setup: STM32F446RE Nucleo + MPU9250 (I2C1, PB8=SCL/PB9=SDA), breadboard wiring, HAL library, 100kHz standard mode.Symptom progression: Sensor works intermittently. When it fails, I see two distinct failure signatures that seem to escalate:First failure mode: HAL_I2C_IsDeviceReady() succeeds (device ACKs its address) but the WHOAMI register read returns the wrong value. After a couple of MCU resets without touching hardware: escalates to the device not ACKing its address at all (IsDeviceReady fails outright).What I've tried:Implemented the STM32 I2C "clear busy flag erratum" workaround (ST-documented fix for the analog filter/BUSY-flag lockup bug — the 15-step GPIO bit-bang + SWRST sequence). This did NOT reliably fix it — worked on some boots, failed on others, no clear pattern. A full power cycle (not just MCU reset — actual power removal) temporarily restores it to working. Reseated all breadboard connections (SDA, SCL, VCC, GND) multiple times — no change in behavior.What this rules

Dear ST Support Team,I am currently working on an LLC resonant converter project using the STM32G474 microcontroller.My goal is to implement Synchronous Rectification (SR) using the STM32G474's PWM timers and Comparator peripherals. However, I am unsure about the correct peripheral configuration and firmware implementation.I would appreciate your guidance on the following: How should I configure the PWM timers and Comparator peripherals in STM32CubeMX for Synchronous Rectification? Which timer and comparator connections are recommended for this application? Are there any reference projects, example firmware, or application notes available for implementing SR on the STM32G474? Are there any recommended CubeMX configurations or firmware examples that demonstrate this functionality? Could you recommend any official documentation, training material, videos, or tutorials that explain the implementation of LLC Synchronous Rectification using STM32? My objective is to understand the c

Hello everyone,I am working on Ethernet communication using the STM32H750B-DK with STM32CubeIDE and LwIP. I am using the onboard LAN8742 Ethernet PHY and a direct Ethernet connection between the PC and the board. LwIP is configured with NO_SYS = 1, and I am continuously calling MX_LWIP_Process() in the main loop. When I check the Ethernet traffic in Wireshark, the PC continuously sends ARP requests asking for the STM32 MAC address, but the STM32 does not send an ARP reply. While debugging the gnetif structure, I see PHYLinkState = 0, speed = 0, and duplex = 0. I also checked the STM32H750B-DK documentation and found that the onboard Ethernet PHY is connected through MII. My CubeMX project was initially configured for RMII, so I changed the Ethernet configuration to MII. I am also checking the Ethernet DMA/LwIP memory configuration and moved the Ethernet descriptor and RX buffer sections to D2 SRAM using the linker script. However, I still cannot get a ping response from the board.Curre

I have two concurrent UART DMA RX running in STM32l431. UART2 is running all the time and UART3 is started when a command is sent and waiting for data. Both of them works, but when I try to make a new DMA transfer on one of them the other stops which I do not want. Why does this happens? Here is the initiation:DMA_HandleTypeDef hdma_rx2;DMA_HandleTypeDef hdma_rx3;DMA_HandleTypeDef hdma_lrx1;DMA_InitTypeDef DMA_InitStructure;void HW_DMA_Init(){ __HAL_RCC_DMA1_FORCE_RESET(); __HAL_RCC_DMA1_RELEASE_RESET(); __HAL_RCC_DMA1_CLK_ENABLE(); __HAL_RCC_DMA2_FORCE_RESET(); __HAL_RCC_DMA2_RELEASE_RESET(); __HAL_RCC_DMA2_CLK_ENABLE(); currentDMABufferWrite = 1; currentDMABufferRead = 0; dmaLen1 = 0; dmaLen2 = 0; dmaHasData1 = false; dmaHasData2 = false; /* Configure the DMA handler for reception process */ hdma_rx2.Instance = DMA1_Channel6; hdma_rx2.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_rx2.Init.PeriphInc = DMA_PINC_DISABLE; hdma_rx2.Init.MemInc

Hello,I am working with an STM32N657 on the NUCLEO-N657X0-Q and I am trying to use the Ethernet PTP PPS signal as a hardware start trigger for TIM3.TIM3 is configured as follows: HAL_TIMEx_TISelection(&htim3, TIM_TIM3_TI1_ETH1_PPS, TIM_CHANNEL_1);sSlaveConfig.SlaveMode = TIM_SLAVEMODE_TRIGGER;sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_RISING;sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1;sSlaveConfig.TriggerFilter = 0;HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig);TIM3 itself uses an external clock on ETR2 and should only be enabled by the rising edge of ETH1_PPS.The internal connection works correctly when I use the normal/fixed PPS mode.For example: ETH1->MACPPSCR = 1U;In this case the PPS rising edge reaches TIM3, TIM3->CR1.CEN becomes set, TIM3 starts counting and the rest of my application starts correctly.However, I cannot get the same internal connection to

HIHow to create a project for STM32H7 with Ethernet and LwIP stack working | CommunityRx buffers labeled “Zero Copy” and are used by DMA and CPU are not marked by MPU for cacheable? only descriptors are. I couldn’t find any special clean or flush cache operations in code as well. Why is that? Image below shows only descriptors (512B) and TX (LWIP heap) are noncacheable.