STM32 MCUs Products

Hello, I am trying to make the lpuart1+dma_linked_list transferring data in stop1 mode.My setup is like this:    SPI1 + GPDMA: // SPI clocked from HSI    Start transfer    Enter STOP    SCK continues toggling    DMA continues    Transfer completes    DMA irq wakes from stopLPUART1 + GPDMA: // LPUART clocked from LSE    Start transfer    Enter STOP    TX line freezes    DMA stops progressing    Exit STOP    TX resumes Both peripherals are using dma in linked list mode in a similar manner.My understanding is that since both peripherals are “autonomous” they should work in a similar way. I have no problem with the SPI1 working during stop1 mode but the LPUART seems to behave differently.This is my LPUART1 init code: void bsp_lpuart_init(void){    bsp_lpuart1_reset_hard();        LL_LPUART_SetPrescaler(LPUART1, LL_LPUART_PRESCALER_DIV1);    // Disable before configuration    LL_LPUART_Disable(LPUART1);    while (LL_LPUART_IsEnabled(LPUART1));    LPUART1->BRR = 3495; //419430    LL_LPUAR

Hardware: STM32N657 + DCMIPP CSI-2 Host (Synopsys DWC D-PHY). Sensor: onsemi AR0144CS, MIPI 2-lane, RAW12 (DT 0x2C), 27 MHz EXTCLK, link ≈  445 Mbps/lane, PHYBitrate = DCMIPP_CSI_PHY_BT_450.  Symptom - the receiver clock lane never enters HS:  - The sensor is definitely streaming: its FRAME_COUNT (0x303A) advances ~58 fps read over I2C; RESET_REGISTER = 0x005C (STREAM=1).  - The CSI host decodes exactly one Frame-Start short packet, then nothing — csi_sof=1, csi_eof=0, framebuffer stays black, and all error  counters are zero (ECC=0, CRC=0, SYNC=0, no SoT errors).  - CSI_SR1 = 0x64100000 → ACTCLF (bit31) = 0 (RM0486 §40.9: ACTCLF = D-PHY_RX RxClkActiveHS). STOPCLF (bit28) = 0. So the clock lane never  reaches sustained HS.  Key control comparison (same board, same DCMIPP/CSI receiver): a Sony IMX708 in continuous-clock mode reaches ACTCLF=1 ("CDR locked") in ~1  ms and captures full frames. Only the AR0144 (which I believe emits a non-continuous/gated clock) fails — ACTCLF stays 0.  Wh

As I understand, the TSSOP20 version needs an external oscillator instead of a 8MHz crystal connected directly to the MCU pins. Is that correct?I'm asking because I have seen a board on AliExpress using this same processor with a 8MHz crystal.

Hi, I have bought STM32H743VGT6 and want to make bootloader and application. The issue is that its memory layout is confusing. In documentation and generated application I see/assume flash memory is:0x8000000 size 0x80000 (512kb bank1?) // bootloader 0x8100000 size 0x80000 (512kb bank2?) // applicationBut when I try to write to 0x8100000 I get "Error occured during memory writing!". Instead I can write to0x8000000 size 0x100000 (1024kb)Does this mean I have only Bank1, but no Bank2? Can I still do bootloader which is on Bank1 and writes to flash on same Bank in different sector? How can it be that I have only one Bank?..

Hi,I already tried to search for previous threads that could help me (like this one), sadly without success.I'm currently studying the ADC peripheral on STM32F3DISCOVERY from the reference manual. I started writing a simple program to measure a tension on PA0. It all works flawlessly until the ADC samples the value on PA0, stores it in the Data Register and raises EOC. From the manual:"The ADC sets the EOC flag as soon as a new regular conversion data is available in theADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared bythe software either by writing 1 to it or by reading ADCx_DR." (page 347, Section 15.3.23).The loop part of my code is the following (I already configured the ADC for single conversion mode, L[3:0] = 0000, DIFSEL=0 and so on... to rule out any problem with configuration):unsigned int ADC_value = 0; while(1){ ADC1->CR |= ADSTART; //wait for EOC=1 while((ADC1->ISR&EOC) != EOC); //Data register read ADC_value = (ADC1

Hello Everyone,During the operation of my program, there will be an issue of address inversion on stm32f030c8.It occurs approximately every 4 hours, and then it transitions to a "hard fault".For example, I was trying to read from address 0x20000940, the register R0 returns 0x20400940, 1 bit was flipped, and it is out of the range of ram address(0x20000000-0x20002000), runs into hardfault in the end.I measured the surface temperature of the chip, and when the problem occurred, the surface temperature of the chip was 65 degrees.I suspect it's a problem caused by excessive temperature, so I used a fan to blow on it. It has been running for a whole day and is still functioning normally.The vcc of the MCU is 3.3V. I used external crystal oscillator 8M, the PLL  Clock is 48MHZ, configuration like follow:    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;/** 使用外部晶振（8mhz） */    RCC_OscInitStruct.HSEState= RCC_HSE_ON;/** 打开高速外部时钟 */    RCC_OscI

G4 ref man says there is 1 (one) FDCAN peripheral:Yet when editing the IOC file I see 2 (two) FDCAN peripherals:I believe the ref man. What's with the IOC file editor?

Hi All,  In my application, I am using the STM32L451RCT6 and trying to configure COMP2 with the internal Vref as a reference (specifically 3/4 Vref). For some reason, it never worked. I was only able to get it working when using DAC_CH1 or an external source as the reference. After a few days of troubleshooting and research, I finally found a relevant block diagram along with an important note in the reference manual (page 532). The thing is, there are no mentions or explanations of this behavior in the reference manual, datasheet, or errata other than this. Could you confirm whether the STM32L45x series actually supports using the internal Vref as a comparator reference or am I facing some other issue here? Thank you!   

Hello, Can someone pls help me fill this information out for STM32H753VIH6? Thank you.      Model NameCheck Group１ (注１)２ (注２)３ (注３)４ (注５)Ministerial Ordinance Article Number第６条第一号イ第６条第一号ロ第６条第一号ハCheck ItemsPresence or Absence of Radiation-Hardened DesignDesign IntentRated Operating Temperature Range (°C) Whether or not compound semiconductors are used (Note 4)Maximum Clock Frequency (Note 4) (MHz)   Determination Criteria(i) Total Ionizing Dose: (Applicable) ≧ 5x10³ Gray (Si)(ii) Dose Rate: (Applicable) ≧ 5x10⁶ Gray (Si)/s(iii) Neutron Flux (1 MeV equivalent): (Applicable) ≧ 5x10¹³ (particles/cm²)Is it designed for civil automobiles or railway vehicles?(i) (Applicable) > 125°C(ii) (Applicable) < -55°C(iii) (Applicable) = -55 to 125°C(Applicable) = Formed from compound semiconductors(Applicable) > 40(Filling Example) ＡＢＣｘｘｘｘｘ－No0～85(Compound)30STM32H753VIH6          &nbs

Hello,   ich set up my project with CubeMX for a CAN-FD (1 MBit/s / 4,8 MBit/s) and a Display for communication. Now i have the problem, that the SCK Signal for the communication looks more like a sawtooth signal than a rectangle. Also the SPI-Prescaler for the baud rate does not affect this signal. i am really confused. I need to use the 48 MHz HSE for my 4,8 MBit/s data phase for CAN-FD. I use an NUCLEO-C092RC and a LCD Display with ILI9341 (library from Mauro De Vecchi) Thanks for the help

Hello. Please check if there are any issues with the settings as shown below. PB4 : SPI1_miso PB3 : SPI1_sck PD6 : SPI1_mosi   Thank you.

MCU : STM32WLE5CCU6Firmware Package Name and Version : STM32Cube FW_WL V1.4.0Application : FUOTA using LoRaWANSetup : End Node(STM32WL) <===> Gateway(Dragino LPS8) <====> TTNHello, I am trying to get my LoRaWAN FUOTA example running for few days with unsuccessful attempts.At first i was successfully able to build LoRaWAN FUOTA application provided by ST under STM32Cube_FW_WL_V1.4.0. This firmware is made for NUCLEO-WL55JC(STM32WL55JC, Dual core with 256KB flash)But as i have STM32WLE5CCU6(Single core 256KB flash). With that also i tried to change the startup and linkers and updating .cproject with correct part number and was able to build it but while flashing gets an error.\STM32Cube\Repository\STM32Cube_FW_WL_V1.4.0\Projects\NUCLEO-WL55JC\Applications\LoRaWAN_FUOTA\Scripts\STM32CubeIDE> .\program.bat ########################################### # 0- Set all global variables ########################################### ######################################

Hello,I have a custom board based on the STM32U5A5 microcontroller. I am trying to run a fingerprint reader sensor over USB on this board. For this project, I am using USBX Azure RTOS.The configurations I made on the CubeMX side are as follows:High Speed Clock: Crystal/Ceramic ResonatorLPUART1 for UART communication:Mode: AsynchronousBaudrate: 115200 Bits/sPB10 -> LPUART1_RXPB11 -> LPUART1_TXUSB_OTG_HS Mode and Configuration:Internal HS PHY -> Host OnlyPA11 -> USB_OTG_HS_DMPA12 -> USB_OTG_HS_DPActive_VBUS -> DisableNVIC Settings -> USB OTG HS Global Interrupt: EnabledPA9 GPIO Output enabled for USB power (I verified that the device is powered correctly.)THREADX Mode and Configuration:Core: EnabledUSBX:Core System -> EnabledUX Host HS -> Host CoreStack HS: EnabledHost Controllers HS: EnabledHID:Core: EnabledKeyboard: EnabledMouse: EnabledClock Configuration:OTG HS Clock Mux: PLL1P enabled and set to 24 MHz (I also tried 16 MHz)Project Manager:Toolchain: STM32C

There seems to be a documentation error between DS14053 Rev 4 and RM0492 Rev 3.  In the data sheet, section 3.17, table 3, "ADC Features" we see a different set of features compared to the reference manual, section 19.3, table 107.  The data sheet claims oversampling up to x1024, a data register of 32 bits and gain compensation is supported.  The reference manual claims oversampling up to x256, a data register of 16 bits and no gain compensation.The register set description only has oversampling fields with values up to 256.  It would be helpful if ST could correct whichever document is wrong, and if the reference manual is wrong and oversampling up to x1024 is supported, then please also correct the register definitions.Thanks,TG

STM32H743VGT6 how to use slave I2C+DMACurrently, this usage is fine. However, when using the DMA function, it will trigger an ER interrupt.HAL_I2C_Slave_Seq_Receive_DMA, How to use it? Are there any examples?// 从机地址匹配回调函数 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { if (hi2c->Instance == I2C1) { if (TransferDirection == I2C_DIRECTION_TRANSMIT) { Rx_len = 0; memset(I2C_rxBuffer,0,4); HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, I2C_rxBuffer, 1, I2C_FIRST_AND_LAST_FRAME); } else { HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, I2C_txBuffer, Tx_len, I2C_FIRST_AND_LAST_FRAME); } } } 

Hi, I'm using the STM32C071K8U6's built-in USB DFU bootloader for one-time production programming. After flashing, PA11/PA12 (USB D+/D-) are used as regular GPIO outputs to control two P-MOSFETs (each with their 100kΩ gate pull-ups to 4.2V).   The USB functionality is not used by the end customer, but the USB connector remains accessible for charging. This means a PC's USB cable may be connected during normal use allowing for potential signal injected into those traces resulting into the PMOS being turned on/off by the PC if it detects there is a USB device connected and tries to enumerate it.   The two core issues: a) When a user plugs into a PC for charging, we need to guarantee the host does not attempt enumeration, and that nothing the host does on D+/D- interferes with our GPIO-driven MOSFET gates. b) because the PA11 and PA12 traces also go all over the PCB - i.e. they form very long stubs - we need to make sure this does not prevent the USB from working properly d

Hello,I would like to ask about the UFQFPN32 package footprint for the STM32G491KEUx device.We are using the following part:Part number: STM32G491KEUxPackage: UFQFPN32While reviewing the datasheet and package information, we found that the actual UFQFPN32 package appears to have an exposed pad (EP) on the bottom side of the package.However, in the datasheet/package information we reviewed, the UFQFPN32 package information and footprint example do not seem to include the EP or the EP land pattern.In particular, the UFQFPN32 package information is shown in the document from page 166 to page 168, but we could not find any information regarding the exposed pad or the recommended PCB land pattern for the EP.Could you please confirm the following?Is the exposed pad information for the STM32G491KEUx UFQFPN32 package omitted from the datasheet/package information?For actual PCB design, should we include an EP land pattern for the UFQFPN32 package?If the EP land pattern should be included, shou

Dear STM Engineer, thank You very much for Your great effort  for the new STM32V8. My comments on the features after looking into stm32v8-presentation.pdf: - STM32V8 will have a ETH-Gb-MAC with PTP, that is great news for applications in the field of scientific instrumentation. -- I am missing PTP-Timestamp-capture-peripherals to generate PTP-precise timestamp input-pulse captures on external events. So triggered by one GPIO input-pulse-edges  (or better several logic-combined GPIOs, at least two to have one "gating), a timestamp (64 Bit or more?) should be stored, including in its timestamp-word at least two (better four or more) GPIO Input-states: state high/low AND edge falling/rising. We would need as many as possible of these PTP-Timestamp-capture-peripherals as possible, e.x. 16 or more of them per MC. Would You consider to include such PTP-Timestamp-capture-peripherals into STM32V8? - -  I am missing PTP-output-pulse-peripherals to generate PTP

ST moderator: post split from this thread. Hello mƎALLEm, Thank you for your confirmation on this issue. I would like to provide some additional information. I have also encountered the same problem on the STM32F405RGT6. In STM32CubeMX, when I configure both HSE or LSE to "Bypass Clock Source" mode, the tool insists on reserving PH1 (OSC_OUT) or PC15 (OSC32_OUT) as RCC pins. It blocks me from configuring them as regular GPIOs, even though the hardware (as you've confirmed) supports it. Furthermore, I tested this on the STM32F446RE and STM32F446RC using the latest CubeMX, the problem still exists on those devices as well. Regarding the internal tickets you mentioned (220390 for documentation, 222721 for CubeMX), may I kindly ask: Has the CubeMX fix (ticket 222721) been implemented in any release yet? If not, is there an estimated timeline for when we can expect this fix? I understand if you cannot share internal details, but any update would be very helpful fo

Hi, We are planning to use STM32H743ZI for our project. Our requirement is to interface a 7-inch LCD touch display with 1024x600 resolution using a 24-bit RGB interface (RGB888) through LTDC. Can STM32H743ZI reliably support this display resolution? Also, what frame rate can realistically be achieved with this configuration? Are there any important hardware or performance considerations before selecting this MCU? Any suggestions or reference designs would be helpful. Thanks.

Hi all, I'm planning to use USB (DFU mode) for production programming of the STM32C071K8U6 — including the very first firmware upload. The board has no external crystal; I intend to rely solely on the internal RC oscillator.   A few questions: 1) Is USB DFU feasible on this specific part without an external crystal? I've read that not all STM32 variants support USB boot without an external crystal (due to clock accuracy requirements for USB). Can anyone confirm whether the STM32C071K8U6's internal oscillator is sufficiently accurate for this?   2) Are there any specific hardware or configuration requirements I should be aware of for first-time USB DFU programming on this part? As the moment I just have the two USB traces connected to the USB connector but no 5V (VBUS) connected anywhere to the micro. I also have a pushbutton on the BOOT0 pin.   3) What USB speed does the built-in bootloader use, and is it possible to force a lower speed? The reason I ask is that the USB

Hi, we have purchased stm32h750vbt6 microcontroller for analog signal validation with 10k potentiometers to integrate with game controller joystick especially joy.cpl using windows 10 OS.   We have dealt with DMA Circular mode configuration pointing cortex-M7 DRAM to 0x30000000 to retrieve the analog signals associated with respective 10k potentiometers. Totally we have four analog pins such as PA0,PC0,PA3 and PC5 from ADC1 & ADC2 with proper distinguished rank allocation alongside desired maximum sampling cycles but although we have altered and tested with different values of this above configuration it ended up with ADC channel leakage which is declared 16 bit ADC.    Moreover we have tried adding external 100nf capacitors to avoid these linkage but failed.    We kindly request you to resolve the ADC channel leakage in our current stm32 Project. Our entire stm32 project attached for your reference and fault identification.  

is there a way to search for which stm32h7 mcus have integrated HS usb phy?the mcu finder product selector doesn't have such filter, is there an app note, a product brief or anything like that?How is one supposed to find such a controller? (besides manually checking all of them)Sometimes this is the main and only selection criteria. I didn't even know that such a feature even exists.I just stumbled uppon when i saw that the stmlink v3 has high speed usb but doesn't use an external usb phy. 

DeviceSTM32H563ZIT6, single binary (no separate bootloader), dual-bank OTASetup Bank1: Current running firmware (original)Bank2: New OTA firmware (potentially corrupted)IWDG: Started in Bank1 before swapOTABootSafetyCheck: In Reset_Handler of every binary buildBKP0R: Boot counter set before swapProblemAfter bank swap, if Bank2 firmware is corrupted and Reset_Handler never executes:  Bank swap → resetCPU reads 0x08000000 → SP (may be valid)CPU reads 0x08000004 → Reset vector (may be valid)CPU jumps to Reset_Handler addressReset_Handler code is corrupted → garbage instructions → crashOTABootSafetyCheck never runsBoot counter never incrementsIWDG fires → reset → same crash → infinite loopRollback never happensBank1 original firmware never recoversDevice is permanently stuck What We Have Tried1. OTABootSafetyCheck in Reset_Handler  asmReset_Handler: ldr r0, =_estack mov sp, r0 bl OTABootSafetyCheck ; before SystemInit and main bl SystemInit bl __libc_init_array bl

Hello,I am designing a high-speed data logging architecture using STM32H743VIHx. I would like the community to validate my DMA architecture and answer specific questions about eMMC access. I did not find answers in the forum and I am also not an expert in microcontroller hardware/software architecture. --- SYSTEM OVERVIEW ---The logging produces a continuous signal sampled by the ADC. I need to log raw data samples along with GPS and IMU data to an eMMC for post-processing.Key parameters:- ADC: 14-bit dual interleaved on PA6 (ADC12_INP3), differential ~10 MSPS effective- eMMC: S32 GB, eMMC 5.1- SDMMC1 in 8-bit MMC mode- IMU: on SPI2 (PB12-15) at 8 kHz- GPS: on UART4 at 115200 baud --- PROPOSED DMA ARCHITECTURE ---Four concurrent DMA paths:1. ADC1+ADC2 interleaved → DMA1_Stream0 → AXI SRAM (ping buffer)Triggered by ADC1 EOC, reads CDR register (32-bit = 2 interleaved samples)Rate: ~20 MB/sPriority: VERY HIGH2. AXI SRAM (pong buffer) → MDMA_Channel0 → SDMMC1 → eMMCTriggered aft