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Specific STM32H7 series MCUs have the DCMI peripheral greyed out in STM32CubeMX version 6.17.0.See this image:Hovering over the peripheral it displays "Not available: DCMI and PSSI are in exclusive choice"I opened a few projects with different MCUs and checked whether the DCMI was greyed out:​​STM32H723ZGIx - WorkingSTM32H725IEKx - WorkingSTM32H730ZBIx - WorkingSTM32H733ZGIx - WorkingSTM32H735IGKx - WorkingSTM32H742BITx - Not workingSTM32H743XGHx - Not workingSTM32H745BGTx - Not workingSTM32H747XGHx - Not workingSTM32H750IBTx - Not workingSTM32H753Allx - Not workingSTM32H755XIHx - Not workingThe PSSI peripheral is notably absent from the list of available peripherals (correctly as per the datasheet) in STM32CubeMX for the parts where DCMI has been disabled.This is clearly a bug in the mutually exclusive check in STM32CubeMX between the DCMI and PSSI, failing on the parts without the PSSI peripheral. See: STM32CubeMX 6.15.0 claims "DCMI and PSSI are in exclusive choice" for STM32H753ZIT

Hey,I want to enable a fast connection with the STM32WB09KE. How do i avoid that the services and characteristics are discoverd every connection? i toughts there was a option for that when using the full ble stack. But whit this firmware and mcu i don’t see it in the STM32CubeMX. So before is start is this possible with this MCU and ble firmware options? Thx in advance! Best regardsMathias 

Hi friends, Does have processors from this family a dedicated input pin as the the input for inner LDO? It will be in the future to supply the inner LDO with the voltage Vcc/2 from the splitter like LM2665 or other. best regards zbynoB

HelloMy Nucleo-H755ZI-Q board disconnected mid-STLINK firmware update, and I am now unable to complete the process.Could you please guide me on the next steps to resolve this? 

I’m designing a tag coil for the ST25DV-04k. I am planning to use the ST25 to harvest NFC energy from a phone tap for a bioimpedance sensor (MAX30002). The ST25DV will then relay the sensor measurement to the phone via NFC again. I used an online calculator to design the tag coil, and these were the parameters I chose. Parameters for tag coilHowever, I am unsure if my quality factor is too high. “59.77” is before coupling, and I assume it will be lower after that. I understand that a high Q is great for energy harvesting, but it can limit the bandwidth and garble communication between the tag and the reader.Is my Q too high right now? If so, what is the optimal Q factor range? Anything else that stands out from my coil design?

Dear Sir/Madam,We use STPS20200CG-TR Schottky diode in our unit. This diode has operating junction temperature range -40C...175C and storage temperature range -65...175C. Our unit must start operating at -55C. Will STPS20200CG-TR operate at -55C ambient temperature without being damaged and which parameters may deteriorate?Thank you,Alex  

The schematic is shown below. I have pulled  down BOOT0 to ground through a jumper ， power supply voltage is normal. Could you please help me check if there is a problem with the MCU configuration。 

Hi everyone,I have one question before starting one project.I am working on information system related to Philippines government services like NBI Clearance. We are thinking future version can also work on small self-service kiosk or information terminal, not only website.Main requirements are:Stable for many yearsFast boot timeLow powerTouch display supportEthernet or Wi-Fi optionQR code scanner supportUSB printer support for receipt or documentI see many people using STM32 in industrial products.Do you think STM32 is good choice for this type of public kiosk?Or better use Linux SBC like Raspberry Pi for easier software development?I want something reliable because government/public service devices may run all day without restart.Anyone already build similar public information kiosk using STM32?Thanks for any advice.

I am using an LDL1117S50R fixed voltage, 5 V regulator. I am regulating down from +12V to +5V. Our +12V supply is clean.It’s a pretty simple circuit; one 1 uF capacitor at the input, and one 100 nF, one 1 uF, and one 4.7 uF capacitor at the output. I don’t need an enormous load; 500 mA is sufficient.It was working great at first, but once I reach a load of about 200 mA, it began oscillating unstably at about 2.2. kHz. See the screenshot below. I was using a Rigol electronic load to test this. This problem also appears to be intermittent. See the screenshots below. It’s fine, and then unstable, and then fine again, and unstable. The period of instability is not consistent. My PCB is good. The input and output caps are close to the pins and I’ve used low ESR ceramic capacitors.Does anyone have any idea what this may be?

Hi!I wonder why ST have chosen to implement a 10 kOhm pull-up (R34) on the clock line of the SD-card?I have seen this on the STM32MP257F-DK board from ST.Normally, you chould not have a 10 kOhm pull-up on the clock signal, only the other data/command signals.That’s the reason why the EMI filters for the SD-card e.g ST products EMIF06-HMC02F2 and EMIF06-MSD02N16 does not any pull-up onto the clock signal. 

I require urgent technical support regarding a VIPer22A-based dual output power supply design (5V/800mA and 12V/200mA).I have designed and manufactured the transformer according to my calculations; however, the power supply is not operating properly. I have attached the following documents for your review:Schematic PCB Layout Transformer Design DataI would appreciate it if you could review the attached files and provide your feedback and recommendations as soon as possible, as this matter is highly urgent and is currently affecting our development schedule.Thank you in advance for your support. I look forward to your prompt respons

Dear ST team,I have configured the ST87M01 for sending +CEREG URCs when registration state changes with AT+CEREG=5.But the modem attaches, but does not sent +CEREG notification (see traces below): Is this a nominal behavior ?AT+CEREG=5OKAT+CEREG=?+CEREG: (0,1,2,3,4,5)OKAT+CEREG?+CEREG: 5,2,"","",,,,"",""OK+CEREG: 0,"","",,,,"",""+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CSCON: 0+CEREG: 0,"","",,,,"",""#STENG: ECID=08507721,SRV1=FFB11868,PLMN=0002F802,EDRX=00000001,PSM=00000000,ENRG=000045D7#SLEEP DRX 2.4s#WAKEUP DRX#STENG: ECID=08507721,SRV1=FFB21868,PLMN=0002F802,EDRX=00000001,PSM=00000000,ENRG=00000016#SLEEP DRX 1.7s#WAKEUP DRX Best regards,Thierry

Hello,I'm currently integrating the SBSFU 2.8 for one of our board, that use a STM32H753, with a dual-slot configuration.I'm adapting the example for the STM32H753ZI. For now, this mostly involves modifying the USART (use the 6 instead of the 3).I am currently trying to set up the system to resume operation after a power outage. I defined ENABLE_IMAGE_STATE_HANDLING in the projects SeCoreBin and SBSFU.This is my scenario:Download of a UserAppValidation of the downloaded UserAppDecryption of the UserAppStart of the swap between the DownloadSlot and the ActiveSlot/!\ Power outage!Power returnResume of the installation processCurrently, the resume always fails when checking the trailer (in CheckTrailerMagic).I checked what he wrote as trailer (in WriteTrailerHeader), and what is written is indeed what is read after the reset.What's strange is how he slices up what he's checking.If we look at the names of the arrays in the CheckTrailerMagic function, we have:FieldValue readm

Hi, I face the problem with the touchgfx frame rate render has drop periodic after 1000ms that make the animation image (wait circle) has choppiness.My project run on custom STM32U5 has 3MB RAM and 4MB FLASH (I don’t use the external memory). The LTDC configuration at 60Hz(24.5Mhz) for screen 800x480 resolution. The signal when screen not update(full)The signal when screen not update(full)The signal when screen not update(zoom in to see the VSYNC signal)The signal when screen not update(zoom in to see the VSYNC signal) The signal when screen animation the imageThe signal when screen animation the imageThe VSYNC signal is perfect at all.You can run the LogicSystemTimingAnalysis.html in .zip then load the .csv file to see the signal. Thanks,Phat 

Hi, Is there a way to disable Boot0 on PA11 on STM32WL33 ? I can’t find any Bytes Option. The only thing I can find, is we can re map PA11 to another pin.Thanks

Hi all,I am bringing up an ISSI IS66WVO8M8DBLL OctalSPI PSRAM (OctaRAM) on an STM32H563VIT6 overOCTOSPI1 in memory-mapped mode (window at 0x90000000). Reads, register access, and"write a location then read it back immediately" all work perfectly. But any SUSTAINEDor SCATTERED write workload corrupts data: rows that are not continuously re-writtenlose their contents within a few seconds, and some writes come back wrong.This matches errata ES0565 section 2.5.12 ("Variable latency is not supported when arefresh collision occurs during a write access to some OctaRAM memories"). I applied thedocumented workaround - forcing FIXED latency in the memory's configuration register -and I run in the documented MTYP=0b011 (Macronix OctaRAM) mode. The corruption persists,byte-for-byte identical, with the workaround correctly applied and verified by read-back.I have reproduced this on TWO separate boards with identical results, so it is not asingle bad device.Has anyone got OCTOSPI memory-mapped WRIT

STP80NF55-06 MARKING is not same datasheet.Product show marking : P80NF55@ 

 Hello,I have inherited some code where a 5kHz 50% PWM is output in center aligned mode using TIM1. CK_PSC is 275MHz, CK_CNT is 137.5MHz (I think) because PSC = 1.The pattern output matches the implementation:  The yellow trace is a GPIO pin that is toggled in the ISR HAL_TIM_PeriodElapsedCallback(). I want to to keep the same 50% duty but half the frequency to 2.5kHz using the prescaler.From the TRM, it seems I just have to modify PSC from 1 to 2. However, when I do this by poking the SFR register using the debugger, I get the following output:  As you can see, the PWM ratio changes but the frequency does not. I’m at a loss to understand why. So would be grateful for any suggestions.Thank you. In case it helps, here’s my register dump. I have no idea what DMAR is that is my next step.  

Hi everyone,I'm working on an STM32 project where UART communication uses DMA for receiving data. The application works correctly after startup, but after running for a few minutes, the UART stops receiving data intermittently.Project details: MCU: STM32F407VG STM32CubeIDE 1.16 HAL drivers UART2 configured with DMA in Normal Mode FreeRTOS enabled I've already tried: Increasing the DMA buffer size. Lowering the baud rate from 115200 to 57600. Verifying the UART wiring. Checking for overrun errors. The DMA interrupt still occurs, but the receive callback is not always executed.Has anyone experienced a similar issue? Is there a recommended way to keep UART DMA reception running continuously?SolutionThe issue was related to how DMA reception was configured.The following changes resolved the problem: Configure the DMA channel in Circular Mode if continuous reception is required. Restart DMA reception inside the HAL_UART_RxCpltCallback() when using Normal Mode. Check for UA

Hello ! I need to replace a burnt-out AL100BXP component! I can't find a retailer anywhere. Is there a compatible component or a supplier that might stock it? Looking forward to any information—thanks

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I am currently using the NUCLEO-H7S3L8 CN2 Type-C port as a USB_OTG_HS embedded PHY host/source.The TCPP03 source path opens successfully, and both the USB stick attachment and port reset are working. After the reset, HPRT reads 0x00001005, which seems to indicate speed=HS and that the port is enabled.However, during the first EP0 SETUP GET_DESCRIPTOR request: HAL_HCD_HC_SubmitRequest() = HAL_OK HAINT = 0x00000001 HCINT = 0x00000080 TXERR = 1 xfer_count = 0 The exact same issue occurs even during a raw HAL EP0 smoke test, prior to involving USBX/FileX.I would like to verify the following points: What is the mandatory clock/power initialization sequence when using the USB_OTG_HS embedded PHY host on the H7S3L8? Is it acceptable to use HSI → PLL3Q for the USBPHYC clock, or is an HSE strictly required? What are the necessary settle/wait conditions after enabling USBHSREG? Are there any required CC/UCPD configurations for the CN2 Type-C/TCPP03 source setup, apart from the PM9

I am working on a project to drive a door using a PMSM motor in position control mode. I am trying to add an emergency brake function. In an emergency, when the operator pushes a button, motor should brake and then return to its starting position without harming anyone.I know there is PWMC_TurnOnLowSides() function (https://community.st.com/t5/stm32-mcus-motor-control/how-can-i-stop-the-motor-urgently/m-p/597309#M8287 ). But it is just stopping the motor, not braking. I have tried this function.As far as I know, there is no such API in position control mode.If I am wrong, is there an API to brake the motor in an emergency? Can anyone help me? Do you have any advice for me?Any information you provide will be welcomed.   Project:ST MCW Ver             : 6.3.2STM32CubeIDE Ver : 1.18.1Driving algorithm      : FOCControl board            : Nucleo-G474REPower board        &

Hello Team,I want to store Binary files in STlink-V3 Or any other model , to flash the target on the field without host PC / Cube Programmer.I came to know , this device model has Bianary / hex file drag and drop feater , would it helpful in my scenario ?If not , Suggets any other option. 

Hello,Has anyone seen ACTCLF permanently stuck at 0 on STM32N6 despite a confirmed HS clock at the input?I have had issues with this for some time and need a little help. Pehraps the following questions could be enligtning.Are there SNPS D-PHY initialization or calibration steps for the clock lane beyond what HAL_DCMIPP_CSI_SetConfig performs? Clock-lane equivalents of the 0xe2–0xe4 DDL registers? Can ST confirm the CSI kernel clock (IC18) is the D-PHY cfg_clk, and its required range? The CCFR encoding caps at ~33 MHz and the DK example uses 20 MHz, but we couldn't find this constraint stated in RM0486. Is PTSR being permanently 0 expected on this silicon? Is there any way to verify test-interface writes landed? What exactly are the conditions for ACTCLF to assert? Does the RX require observing a complete LP-11 to LP-01 to LP-00 entry sequence after PEN, and is there a known failure mode if the LP levels at the pad are degraded (e.g., loaded by an external common-mode filter) while HS