Solved

Hello,I’m using the SBSFU by MCUboot implementation from the STM32CubeU5 Project (here).It works well on the target board (U585) and I succeeded at uploading a new firmware through Teraterm, as per the documentation :  But our teams cannot all have access to a PC with Windows, and as such I attempted to make an upload with Minicom on Linux (Ubuntu) instead, which did not work (I added the “Bytes” logging before the “Abort from user” message) :  I saw much discussions about a similar problem on the legacy SBSFU 2.4 / 2.7 (this one or this one for example), but none for the one using MCUboot. I’ve still tried most of the solutions proposed there, but to no avail. I’ve tried fiddling around the code to see why the Ymodem protocol was failing through Minicom, but haven’t found much actionable information up to now.Has anyone encountered this problem and may know how to patch it or work around it ?I’ll continue to investigate on my end and document my eventual findings here. Thanks in advan

Hi,I encountered problems during the development process of using FMAC. To illustrate the problem simply, I used FMAC to implement an RC filter, by which I mean to illustrate the calculation problems of FMAC.RC filter:10K+10nFIts discrete z-domain expression：（Ts=1e-6,Tustin）so I get fixed-point parameters :I referred to the example program of AN5305 and used a 1-us timer to trigger ADC sampling. After the ADC sampling is completed, DMA writes to the WriteData of FMAC, and then the ReadData is processed in the interrupt as follows:As shown above, my current ADC sample is 0, and my Vref is set to 800. I think the output of FMAC as an RC filter should be around 800 in the DC case, but actually it is not. It is a relatively small value. Why is that?May I ask if there is a problem with my configuration of FMAC?  

Dear Gentlemen,as a relative beginner using STM32C5 MCU-s,I need your help to resolve one issue.Namely,In new design,  where planned MCU is STM32C542CCT6 device, (LQFP48 package),I plan to use internal Comparator COMP2.Problem (for me) arises when I have to declare connection between Comparator nodes(INP-  (M), INP + (P) and OUTPUT) with some specific pins on LQFP48 package,    more precisely it would be ideal for me to use PA7 pin as Comparator2 Outputand pin PA2 as Comparator2 -INPut, and pin PA3 as Comparator2 +INPut.In short,it is not a problem to "connect" Comparator Output, COMP2_OUT as shown in Table 12 STM32C542xx pin/ball definition, on STM32C542xx data sheet (DS), page 41, or in Table 13 Alternate functions, since i will declare AF14 = COMP2_OUT in appropriate GPIOA_AFRL register, see page 352 in RM0522 Reference manual, (RM)but I have problem to declare Comparator2 INPut pins, since it is selected thru peripheral registers,as stated in Table 11 in device DS, ...Additional fu

Discrepancy between AN5967 and MB1940 schematic regarding VDDA18PMU / VDDSMPS connections in external SMPS mode Hello ST Team,We have a custom board based on the STM32N657X0H3Q, designed using the MB1940 (Nucleo-N657X0Q) schematic as reference. The board has been fabricated and assembled, and we are currently in the bring-up phase.During bring-up we encountered a failure on the external SMPS path (TPS62088YFP) used for VDDCORE generation. The external buck failed with a shorted high-side FET, driving 5V directly onto the VDDCORE rail. After investigation, we recovered the board by removing the failed external buck and switching to the on-chip internal SMPS, which is currently working correctly and supplying VDDCORE at 0.810 V.While reviewing the power supply architecture during this debug, we noticed a discrepancy between AN5967 (Getting started with hardware development for STM32N6 MCUs) and the MB1940 reference design that we would like clarification on.DiscrepancyAN5967, Sectio

hello,When using MDMA (STM32H753), and more than one transfer, the code generated doesn't align correctly the struct MDMA_LinkNodeTypeDef. This structure should be aligned with 64 bits.Please, see : https://community.st.com/t5/stm32-mcus-embedded-software/stm32h753zi-mdma-issue-with-linked-list-dma-adc/m-p/897390CubeMX : V6.17Thanks,best regards,Laurent  

the STM32L431 can trigger per 0.102S by WDI,  but WDO always have a reset signal, why ?   

I am trying to disable the write protection on an STM32G431K (on a Nucleo-G431KB) by settings the option bytes using CubeProgrammer:However, “Apply” fails with the log showing:11:14:40:365 : Option byte command : -ob WRP1A_STRT=0x3f WRP1A_END=0x0 11:14:40:367 : qCmd : -ob WRP1A_STRT=0x3f WRP1A_END=0x0 11:14:40:367 : PROGRAMMING OPTION BYTES AREA ...11:14:40:368 : Database: Config 0 is active.11:14:40:368 : Bank : 0x0011:14:40:368 : Address : 0x40022020 11:14:40:368 : Size : 84 Bytes11:14:40:373 : halt ap 0 11:14:40:381 : Loader write option bytes...11:14:40:381 : Init flashloader...11:14:40:381 : halt ap 0 11:14:40:389 : run ap 0 11:14:40:390 : halt ap 0 11:14:40:396 : run ap 0 11:14:40:420 : Reconnecting...11:14:41:549 : ST-LINK SN : 00190036313351123630373911:14:41:549 : ST-LINK FW : V3J17M1011:14:41:549 : Board : NUCLEO-G431KB11:14:41:550 : Voltage : 3.27V11:14:41:739 : Error: Unable to get core ID11:14:41:739 : Error: Cannot connect to acce

hiI installed version 5.1.1 today and reactivated the license key, but I got the following error. nanoedge ai studio license has reached its activation limit Is there a solution?   I installed version 5.1.1 today and reactivated the license key, but I got the following error. Is there a solution?

Pls help with FIT rate value for below components:STM32N657X0H3Q    - MCU LSM6DSVTR          - IMU Sensor M24M01E-FMN6TP    - EEPROM ST4SI2M0004TPIFW    - eSIM

For the SMPS mode of the STM32H563MIY3Q, the datasheet recommends an inductor with an RMS current (Irms) rating of 1.4 A. However, the actual core current is only 50 mA. Is it acceptable to select an inductor with a lower Irms rating, such as 500 mA?

Hi,what would be recommended way to override internal LDO which is used for VDD11/VCAP preparation? Because of thermal management, we prepared external LDO to lower internal MCU temperature. In H5 family, there was an BYPASS bit in PWR management. Maybe shall I change Vos to lower level to let higher level LDO win? Or would you have other way :) Thanks!JM

Hello,I am using the ST25R200 evaluation board with the STSW-ST25R020 firmware package.I am planning to develop a custom Python GUI that displays a specific text string whenever an NFC tag is detected by the board. To achieve this, I want to modify the C firmware so it actively streams out a text string via UART/VCP as soon as a tag enters the field.Could you please guide me on the following?Which specific source file and function in the STSW-ST25R020 package handle the successful tag detection/inventory loop where the tag's UID is retrieved? Where is the best place to insert a custom printf or logging function to stream this text data out via UART immediately upon detection? Thank you very much for your help!

Hi,the cubemx HRTIM configuration will not let me set the set sources for Output 2, even though deadtime insertion is turned off.I had previously enabled it, and now disabled it. Since then I am unable to add a set source for Output 2.See the attached screenshots and .ioc file.I am using version 6.17.0

I'm investigating a suspected flash corruption/ECC issue on an STM32H743.A read from flash address 0x081F0000 consistently causes a fault. The problem is that I'm not fully confident that the fault status registers can be trusted after the event, so I'm looking for a diagnostic approach that does not rely entirely on the captured fault information.Known facts:Accessing 0x081F0000 triggers a fault. ECC_FA2R does not show a failing address. STM32H7 flash ECC is evaluated only when flash is read. ECC granularity is 32 bytes (256 bits).My main question is:If I suspect flash corruption or an ECC problem, but do not fully trust the contents of CFSR, HFSR, BFAR, SR2, or ECC_FA2R after the fault, what is the recommended way to diagnose the problem?Would you:Perform a controlled BusFault-protected flash scan in 32-byte steps? Use HAL_FLASHEx_ComputeCRC() over the suspect region? Dump the entire flash bank via SWD/JTAG and verify externally? Use some other method?Has anyone seen a corrupted flas

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hi, Could you please confirm whether an external NFC antenna can be connected to the X-NUCLEO-NFC08A1 board? I see P200 and P202 in the schematic, but it is not clear to me whether these are intended for external antenna connection or only for optional/test points. If an external antenna can be used, could you explain how the on-board etched PCB antenna should be disconnected from the ST25R3916B antenna path, where the external antenna should be connected instead, and what antenna inductance or electrical parameters should be targeted before tuning the matching network?Thanks!Best regards, Jose 

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic: For reference, we are used the external loader implementation for development board from the following link: https://controllerstech.com/w25q-flash-series-part-8-quadspi-external-loader/ We request your support in:Verifying if our schematic connections for the QSPI interface may be contributing to the issue.Identifying any possible hardware or configuration-related causes for the external loader failure.

Hi We are developing a board with the STM32U073CCT6 CPU. Would it be possible to use a crystal with the following characteristics for the LSE?32.768KHz Cl=6pF/ESR=50kRIn this case, what would be the recommended capacitor values?BRGilberto 

Hello, I am trying to connect to the STM32F072C8T6 microcontroller via USB in the STM32CubeProgrammer, however I am getting:"Device is under read out protection ! If you want to disable RDP please reconnect with Read Unprotect enabled"So, when I check the Read Unprotect (MCU) checkbox, I get:"Please Power off Power on your device."After turning the power off/on, I see the same messages. I cannot connect to the MCU via USB in the STM32CubeProgrammer.I have tried different versions of STM32CubeProgrammer:v2.16.0v2.15.0v.2.13.0v.2.10.0v.2.8.0Moreover I tried on second computer with Windows 11 and I have the same issue.I'm trying to connect my custom board, but I also checked another hardware board (BluePill ) with the same STM32F072C8T6 MCU and it doesn't work either.Interestingly, using the DFU-util v0.8 program I can connect to the MCU and successfully read/write memory:  

I am using ADXL203  analog inclinometer. I would to compensate the offset variation with temperature.As the ADXL203 itself does not have an internal temperature sensor, could you give me any advice on how to measure the temperature?Thank anybody for the attention.GF 

hifor stm32G4 series, if MCU option byte IWDG_SW equal TRUE, and the software start the IWDG by calling HAL_IWDG_Init(),when a system reset happen( for example, call HAL_NVIC_SystemReset() or IWDG reset), will IWDG stop counting before  next time initialization?  

Hello, I have a STM32F401RCT connected to a ST25R100.In the ioc file I enabled the X-CUBE-NFC9 library with all the necesary dependencies.All the IOs also have pins assigned to them.Plus Pull ups enabled on the IRQ (open drain) and NFC_Reset.Currently I have found out that it crashes somewhere after MX_X_CUBE_NFC9_Init();ret code: 0NFC BSP COM = 100Welcome to X-NUCLEO-NFC09A1 entered error handlerThis is what I get in my console. I added some printfs in the code already.When I run it in debug mode to check were it calls the error handler it for some reason does not hit the error handler but it gets stuck in stm32F4xx_il_usb.c; when I click pauze, this seems rather odd.HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num){ __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { count++; if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Flush TX Fifo

Hi, I met a strange issue of ADC overrun during flash erase.The ADC is configured with circular DMA+TIM3 triggered at 1khz:static void ADC_Config(void) { /* Enable clock */ RCC->AHBENR |= RCC_AHBENR_DMA1EN; RCC->APBENR2 |= RCC_APBENR2_ADCEN; RCC->APBENR1 |= RCC_APBENR1_TIM3EN; /* ADC Init */ ADC1->CR |= ADC_CR_ADVREGEN; uint32_t tick = SysTick->VAL; /* Startup delay */ while ((tick - SysTick->VAL) < 960); /* Calibration */ ADC1->CR |= ADC_CR_ADCAL; while (ADC1->CR & ADC_CR_ADCAL); /* TIM3 trigger, DMA enable */ ADC1->CFGR1 = ADC_CFGR1_EXTEN_0 | 3 << ADC_CFGR1_EXTSEL_Pos | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN; /* Use 14MHz ADC clock */ ADC1->CFGR2 = ADC_CFGR2_CKMODE_0; /* Enable overrun interrupt */ ADC1->IER = ADC_IER_OVRIE; /* Long sampling time */ ADC1->SMPR = ADC_SMPR_SMP1_0 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_2; /* Vref and Tint enable */ ADC1->CHSELR = ADC_CHSELR_CHSEL

HiI'm looking for STM32 Nucleo boards or similar microcontroller boards that have embedded SIM (eSIM) capabilities. However, I haven't been able to find any boards that directly support eSIM integration. Are there any Nucleo boards that are compatible with eSIM modules like ST4SIM, and how can I identify or find them?Thanks and Regards@avbST 

Hi, according STM32H743 datasheet VDDLDO pin in BGA packages can be supplied independently from VDD pins. The problem is that on STM32H743VIH BGA package VDDLDO and VDD physically shorted in the package. Is the datasheet misleading or I’m missing  something?