Question
STM32N6 CSI-2: No frame lock
Hello,
Has anyone seen ACTCLF permanently stuck at 0 on STM32N6 despite a confirmed HS clock at the input?
I have had issues with this for some time and need a little help. Pehraps the following questions could be enligtning.
- Are there SNPS D-PHY initialization or calibration steps for the clock lane beyond what HAL_DCMIPP_CSI_SetConfig performs? Clock-lane equivalents of the 0xe2–0xe4 DDL registers?
- Can ST confirm the CSI kernel clock (IC18) is the D-PHY cfg_clk, and its required range? The CCFR encoding caps at ~33 MHz and the DK example uses 20 MHz, but we couldn't find this constraint stated in RM0486.
- Is PTSR being permanently 0 expected on this silicon? Is there any way to verify test-interface writes landed?
- What exactly are the conditions for ACTCLF to assert? Does the RX require observing a complete LP-11 to LP-01 to LP-00 entry sequence after PEN, and is there a known failure mode if the LP levels at the pad are degraded (e.g., loaded by an external common-mode filter) while HS amplitude is fine?
- Any relevant errata for the CSI D-PHY on STM32N657?
Lots of questions, I know. Its just all I can think of to find a solution. Extra info below.
Hardware: STM32N657X0HxQ + Sony 12MP image sensor, 1-lane CSI-2, 1188 Mbps (27 MHz INCK * 44), continuous HS clock mode.
Problem:
- The D-PHY clock CDR never acquires.
- CSI_SR1.ACTCLF (bit31) = 0 in every run across many changes/improves.
- SOF0F always 0.
- ERR1/ERR2 OR-accumulated are 0x00. No error bits of any kind: total silence.
What IS working (verified):
- Sensor streaming confirmed by I2C readback and oscilloscope at the sensor.
- HS clock physically reaches the STM32N6 pads
- Intra-pair skew measured at 3-7 ps vs the 126 ps budget
- ULPS is fine
Thanks!!