NUCLEO_F429ZI MCO2 is not working

New.Fish · ‎2019-09-30

I have a NUCLEO_F429ZI board, I try to use the MCO2 output 50Mhz clock, but this function doesn't work.

Please refer to the attached project, the IDE is TrueStudio and code generator tool is STM32Cube 5.0.0.

I'm not sure this is my boards fault or F429ZI doesn't support MCO2 clock output.

Regards

Samuel

waclawek.jan · ‎2019-09-30

In debugger, read out and check/post the relevant RCC and GPIO registers.

JW

New.Fish · ‎2019-10-01

Hi,

This board without external crystal, so it can't generate PLLI2S.

HSI can only generate lower than 48Mhz clock.

HSE can generate high frequency clock upto 180 Mhz.

I try use SYSCLK 48 Mhz, MCO2 can get 48Mhz clock.

But use PLLI2S, MCO2 has no clock output, even try 10Mhz.

Please check the F407 reference manual (DM0031020.pdf), chapter 6.2.10

Sam

waclawek.jan · ‎2019-10-01

I don't understand, what do you want to achieve, and what is what you can't do.

All 3 PLLs are fed from the same source, and it's divided HSI or HSE. You can divide HSI to 1MHz-2 MHz exactly as you can HSE, so I don't see any reason why you shouldn't be able to achieve the same PLL output with HSI as you would with HSE.

Again, read out and post the content of relevant RCC and GPIO registers.

JW

New.Fish · ‎2019-10-01

I would like to get accurate 50Mhz clock for Ethernet PHY, the only clock source is from PLLI2SCLK.

My reading for RCC and GPIO register content can't solve my problem, so I read the reference manual.

The reference manual says the highest clock frequency get from HSI is 48Mhz. HSE can up to 168Mhz.

I will buy a crystal for this board later to fix this problem.

Thanks for your reply.

Sam

waclawek.jan · ‎2019-10-01

> The reference manual says the highest clock frequency get from HSI is 48Mhz.

Where exactly does it say that?

> My reading for RCC and GPIO register content can't solve my problem,

Well, if you'd read them and post their content, we could discuss this over. But It's up to you of course.

Regardless of that, HSI is not precise enough for ETH anyway.

On the Nucleo board you could use the 8MHz output from STLink as an input to HSE in bypass mode. By default, it's connected (see MCO from ST-LINK section in OSC clock supply chapter in UM1974).

But not even that is needed - the onboard ETH PHY, LAN8742A, has a crystal connected, and can source the 50MHz clock. Read the LAN8742A manual and the Nucleo-144 manual.

JW

New.Fish · ‎2019-10-01

There is 8Mhz clock in MCU pin PF0/PH0, many thanks for your indication!!!!!!

I know the PHY runs 50 Mhz clock and feeds to MCU PA1, I intentionally use MCO2 output 50Mhz to test other feature.

There are four source to get MCO2, SYSCLK, HSE, PLLCLK, PLLI2SCLK. I test all and find only PLLI2SCLK does't work.

I run single step and monitor the output by oscilloscope,

when it goes to "HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_PLLCLK, RCC_MCODIV_2);" the MCO2 should output correct clock.

But for option " PLLI2SCLK", the MCO2 output 96Mhz clock for 1.2uS then goes low.

The capture registers in attached bitmap file, and the whole project is attached as well.

Do you have this board in your hand? Please try it if you get the time.

Regards

Sam

waclawek.jan · ‎2019-10-02

This is hummm.

Everything appears to be OK - input clock is HSE bypass, PLL input set to HSE, M is 4 i.e. input frequency to PLL is 2MHz which is within range, N for PLLI2S is 192 resulting in VCO frequency of 384MHz which is within range, R divider is 2, resulting in 192MHz which is within range... I don't see any problem here.

> But for option " PLLI2SCLK", the MCO2 output 96Mhz clock for 1.2uS then goes low.

Is there anything connected on MOC2 pin (except for the oscilloscope/LA)? Is there anything else in the program after swithing on MCO2?

What is the power supply voltage next to the mcu pins? Can you have a look at it using the oscilloscope?

Can you try with a lower N for PLLI2S, perhaps half of that what is now?

JW

Dave Nadler · ‎2019-10-05

@New.Fish - Please see the following for info about how to work around CubeMX bugs to get MCO2 output:

https://community.st.com/s/question/0D50X0000BQQPIJSQ5/bug-cubemxgenerated-code-fails-to-properly-initialize-plli2s-mco2-etc

Hope that helps,

Best Regards, Dave

waclawek.jan · ‎2019-10-05

Indeed - as Dave found out, the bug causes the Cube/HAL function for setting PLLI2S is ineffective for the 'F4x7/4x9.

I misinterpreted the register values above: RCC_PLLI2SCFGR is in its reset setting (which is incidentally sane), and I did not notice that PLLI2SON in RCC_CR is 0...

JW