How to configure Octospi as a normal Spi interface (Not interfacing with external memory devices)?

[MFolk.1]

I am programing the STM32L4S9AII6 using the STM32L4R9I-EVAL board. My application requires the use of 5 different SPI buses, but the STM32L4S9AII6 only has 3 standard SPIs. However, it has 2 Octospi buses that I understand can be configured to be standard SPIs. Is this true or have I been mislead? Can someone shed some light on how to configure an Octospi as a standard full-duplex spi? Preferably using MxCube.

 

More specifically, I want it to be equivalent to this standard SPI configuration:

[MFolk.1]

[Andreas Bolsch · Accepted solution]

Just read RM0432, section 19.4.3. Instruction, address, alternate are "send to slave only", dummy is nothing at all, data is either "send to slave only" or "read from slave only" (depending on memory-mapped/indirect write or read).

The diagrams below are just for brevity, instead of showing two separate diagrams for both directions, they're combined into one. That's well-known and well-established convention, see e.g. datasheet of MC6821, Fig. 1 Bus timing as of 1985(!!!).

[Tesla DeLorean]

I'm a read behind/between the lines guy, with a background in IC design and validation.

It's the absence of anything supporting concurrent operation that is the most glaring here. The complexity of the implementation and the diagrams would be around 2x if the FIFO and registers were capable of sustaining duplex operation, the status and control also lack. The IC designers are going to choose the least complex/least transistor approach unless beaten by management to burn more resources. Efficiency and elegance of the design is where you shine in the team

See USB, it's also one of these things where the channel is unidirectional in operation, but can switch.

[duke29]

im not sure but that and  you can try the following plan to imeplement  the full duplex  mllti  spi which transport byte revelop to the bit at each channel .

 the menu dm00407776 show that  the  octoSPI 1/2 in common clock source hence user can use octoSPI 1 as “muli  MISO  ”and octoSPI2 “as muli  MOSI ”  vice versa   ，octoSPI1/2  driven by same time sequence  to fulfil full duplex SPI

that is feasible or ont depend on the specific characteristic of  target chip