Inconsistency in WWDG_CFR description for STM32G0xx and STM32C0xx

[Andreas Bolsch]

RM0444 rev. 5, sec. 29.3.4 and RM0490 rev. 3, sec. 21.3.4 both employ only WDGTB[1:0], but WWDG_CFR description mentions WDGTB[2:0] with eight different prescaler settings. So actually two or three bits?

[Peter BENSCH · Accepted solution]

Thank you for bringing this to our attention!

That indeed looks like a copy'n'paste typo. In fact, the time base of the WWDG has been extended compared to previous implementations and has three bits. The text strings WDGTB[1:0] still to be found in these RM should therefore be read as WDGTB[2:0].

Regards

/Peter

@Imen DAHMEN​ 

[Imen.D]

Hello All,

Thank you for rising this up.

Internal ticket (ID 154205) is submitted to correct the typos in RM0444 and RM0490.

(PS: ID 154205 is an internal tracking number and is not accessible or usable by customers).

Imen