HRTIM STM32H743 for 3-phase control - shadowing register

[DrDro]

Hallo there,

I use HRTIM_MASTER to retrigger HRTIM A,B;C and to trigger ADC. This works fine.

Each of slave timers generate PWM signals. I works also good.

As the data from ADC is ready I do recalculation of PWM duty for all 3 channels. And there is an issue.

Shadow registry and update on counter reset (bit TxRSTU) should be executed only if all three values are ready. Sometimes I get faulty PWM because third PWM value is not recalculated but gets updated together with first already calculated duty for A and B.

How can I implement double condition of shadow update: once as all 3 dury are new calculated and on counter reload (to keep PWM cycle consistency).

[Pierre_Paris]

Hello @DrDro,

Thank you for your question !

1/ "I do recalculation of PWM duty for all 3 channels" -> So you are using the DMA burst controller to update the CMP1xR for example to control the Duty Cycle of the PWM "on the fly" ?

2/ "should be executed only if all three values are ready." -> How are you using the ADC ? Maybe add a condition that wait the EOC (end of regular conversion) or EOS (end of sequence) flags before updating register ?

3/ What's your application ? You want to update dynamically the duty cycle, that's it right ? Can you please share your code or the logic ?

You can find here the AN4539 about the HRTIM and operating modes. Are you aware of this doc ?

Best Regards,

Pierre

[DrDro]

Thank you your quick reaction.

1/ No DMA for PWM is used. I write CMP registers in interrupt context directly, roughly like that:

sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = m_duty_begin_A

sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP2xR = m_duty_end_A

... the same for B and C

All that happens on HAL_ADC_ConvCpltCallback() callback, i.e. when ADC data are ready and DMA transfered to RAM.The code inside this callback is comlex, spreaded between many classes, it would be difficult to cut it out and post here.

2/ There is no issue with ADC, data are converted correctly and EOC is reported, as mentioned above, with help of callback (interrupt)

3/ The application is advanced PMSM motor driver, including high resolution PWM (HRTIM), 3x ADC current measurement, voltage, speed, torque controll.

Yes, I'm already familiar with HRTIM cookbook. I could not find the aswer, how to update CMP registers on timer reset/roll-over (preventing PWM corruption) but only as all three Timer shadow registers are updated (once after software trigger).

[Pierre_Paris · Accepted solution]

Hello @DrDro,

Your welcome, my pleasure !

Q : How to update CMP registers on timer reset/roll-over (preventing PWM corruption) but only as all three Timer shadow registers are updated (once after software trigger) ?

A : According to RM0399, and regarding your application, I advise you to perform Burst DMA transfers (explanation chapter 39.3.21) with the coherent update below. The principle is to reprogram dynamically which CMPx registers are to be written by DMA.

 When the preload is enabled (PREEN bit set), there are 3 use cases:

• I think, the one that interest you is this one : "The update is done on the update event following the DMA burst transfer completion (UPDGAT[3:0] = 0010 in HRTIM_TIMxCR and BRSTDMA[1:0] = 10 in HRTIM_MCR). This mode guarantees both a coherent update of all transferred data and the synchronization with regular update events, with the timer counter. In this case, if a regular update request occurs while the transfer is on-going, it will be discarded and the effective update will happen on the next coming update request."

Did I answer your question ?

Best Regards,

Pierre

[DrDro]

Hello Pierre,

it sounds good for me. I'm just trying to impement it with HAL library. Not an easy task. Is there maybe example code based on HAL functions?

Best Regards