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STM32H7 traceclkin source

drath
Associate

Hi all,

I'm trying to understand what source the STM32H7 (specifically STM32H743) uses for the TPIU trace clock.

According to the RCC chapter there ought to be a multiplexer that allows to choose from a number of sources:

drath_0-1728309614149.png

According to the debug chapter, it is derived from the pll1_r_ck (no mention of the other options show above):

drath_1-1728309679906.png

Is this clock multiplexer for traceclkin actually implemented, or is it fixed to pll1_r_ck? If this multiplexer is actually implemented, how is it controlled, i.e. which register/bits?

Best Regards,

Dominic

 

1 ACCEPTED SOLUTION

Accepted Solutions

Indeed, The Clock source is controlled by SW field in RCC_CFGR register. A field common to both System clock and trace clock:

SofLit_0-1728984429189.png

SofLit_0-1728984683206.png

And if the system clock is on PLL1_p trace clock will be on PLL1_r otherwise it will be on HSE, HSI or CSI.

So please mark the solution.

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

View solution in original post

3 REPLIES 3
SofLit
ST Employee

Hello @drath and welcome to the community.

I'm checking internally and get back to you as soon as I have a feedback (internal ticket number for follow-up 193043)

Thank you for this contribution.

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

I believe I can answer my own question:

The traceclkin switch is controlled by RCC_CFGR[SW]. While that field is documented to switch the system clock (sys_ck), I guess we can assume that this actually switches both sys_ck and traceclkin in parallel. This is what the blockdiagram shows and it matches our observations, even if the RCC_CFGR documentation doesn't explicitly mention it.

Regards,

Dominic

Indeed, The Clock source is controlled by SW field in RCC_CFGR register. A field common to both System clock and trace clock:

SofLit_0-1728984429189.png

SofLit_0-1728984683206.png

And if the system clock is on PLL1_p trace clock will be on PLL1_r otherwise it will be on HSE, HSI or CSI.

So please mark the solution.

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.