Hello @Ditzhak, Thank you for your question and please don't hesitate to create a specific thread for this subject ! In an ADC configuration where multiple channels are being sampled, the sampling time for each channel can be affected by the number o...
Hello @OJ,Thanks for your question and feedback !"This gives the impression that you can clear HRTIM_ISR bits by writing to this register (HRTIM_ISR)" -> Indeed, you are right, the sentence is ambiguous. We will specifies the register HRTIM_ICR for n...
Hello @arjun.binu,I appreciate all the documents you gave, please don't hesitate to contact your local FAE for any other support !I didn't see obvious reason until now but I have some remarks :I don't think your issue is coming from IWDG. But if you ...
Hello @arjun.binu,Here some points :Only in one device, the core is failing to run the core [Firmware not executing]. The other device continues to operate fine and the core is running. -> If you applied the same OB configuration with the same firmwa...
