2019-09-20 07:11 AM
I am using HSI as a system clock and PLLSAI1R ADC clock.
With PLL, ADC1 clock value becomes 80 MHz.
I am using End of conversion interrupt in continuous conversion mode on the channel 5.
How can I measure sampling rate of the ADC,?
2019-09-20 07:54 AM
Use a relatively high-impedance ADC input source and observe the ADC pin using an oscilloscope. You'll see the sampling as thin pulses as the sampling capacitor charges.
Other option is sofware: set up a DMA to convert some number of samples, and duration of that number of conversion will give you the sampling rate.
JW
2019-09-20 07:59 AM
+1
Time Stamp the DMA completion, or toggle a GPIO and scope it
or work the math on the clocks/settings, it's all gear ratios.
Usually if you want defined timing, you use a TIM to trigger the ADC, and set the ADC to optimal speed/performance settings to meet delivery deadlines.