STM32G030F6P ADC Frequency in STM32CubeMX

[MKanc.1]

I was checking maximum frequencies of some MCUs and noticed i can pick ADC frequency in CubeMX clock configuration up to 80MHz for TSSOP-20 STM32G030. Its maximum frequency is 64MHz.

Datasheet states it can deliver maximum 2Msps on 12 bit but with its 1.5 Sampling and 12.5 conversion cycles it reaches way higher sample rates.

I checked some of the reference manual chapters and did not noticed anything unusual, prescalers seems to accept /1 divisions as well.

I am not familiar with reference manuals. Datasheet 5.3.17 also shows 35MHz maximum frequency. What's the thing i am missing? Is it a bug on interface?

[Imen.D]

Hello @MKanc.1 ,

The maximum frequency of STM32G030 is 64MHz as mentioned in the Datasheet.

Which CubeMX version used?

[MKanc.1]

I had 6.12.x something before, updated to 6.13.0 and it is still same.

Stm32CubeIDE 1.16.1 have same issue, accepting ADC frequency up to 80 MHz.

[Imen.D]

Hi @MKanc.1 ,

An internal ticket (ID 201535) is submitted to fix this.

Thank you for your contribution and for bringing this issue to our attention.

(PS: internal ticket ID 201535 is an internal tracking number and is not accessible or usable by customers).

[Imen.D]

Hello @MKanc.1 

This issue is fixed in the latest release of CubeMX v6.15.0.

Thank you for your contributions.

[Ozone]

> ...CubeMX clock configuration up to 80MHz for TSSOP-20 STM32G030. Its maximum frequency is 64MHz.

> I am not familiar with reference manuals. Datasheet 5.3.17 also shows 35MHz maximum frequency. What's the thing i am missing? Is it a bug on interface?

Those are the maximal clock frequencies for the ADC peripheral units, not sampling rates. You probably noticed.

> I checked some of the reference manual chapters ...

I would highly suggest to read the full ADC section of the reference manual, it describes this unit in detail - including all the sequential steps involved until you get the ADC output.

Other STM32 devices have several ADC units that can work in interleaved mode, and thus doubling or tripling the effective sampling rate.
However, designing proper analogue hardware to support such high sampling rates with acceptable accuracy is far from trivial either.