Associate III

Question

ADC Sampling Rate for STM32G431: Practical vs Theoretical measurements

Forum|Forum|1 year ago
January 8, 2025
13 replies
4290 views

Hello STM Community,

I am working with the STM32G431 microcontroller and have encountered a discrepancy between the practical and theoretical ADC sampling rates. Here's my setup:

ADC Input: PA0 configured as ADC1_IN1 (single-ended mode).
ADC Parameters:
- Mode: IN1 Single Ended
- ADC Prescaler: Synchronous Clock Mode Divided by 4
- Resolution: 12 bits
- Data Alignment: Right
- Continuous Conversion Mode: Enabled
- Sample Time: 2.4 ADC Cycles
System Clock Frequency: 170 MHz

I have toggled a GPIO pin after ADC conversion to observe the sampling rate on an oscilloscope. The measured sampling rate is approximately 142 kHz, while my theoretical calculation suggests it should be around 11.33 MHz.

The theoretical calculation considers the formula:
Sampling Rate=fADC /{ [sampling time(in cycles)] + [resolution (in bits)] +(0.5)}
Substituting the values:
Sampling Rate=170 MHz / (2.4+12+0.5) ≈ 11.33 MHz

I am unable to identify why there is such a significant difference between the calculated and observed rates. Could it be due to additional overhead, configuration issues, or something else I'm overlooking?

Any insights or suggestions to help resolve this would be greatly appreciated!

Thank you!

This topic has been closed for replies.

AScha.3

Super User

Hi,

1. how you get the idea, the ADC would convert at 11MHz speed ?

Look at ds : absolute max. speed at 12bits is 4 Mhz :

2. The ADC is clocked, so it will convert at the speed you set it - not only theoretical .

Now your measured speed is a bit slow, so you set it very wrong.

3. Read ds + manual , to see how to use it. And dont forget calibration .

Or look at examples from STM , and app.notes ANxxx , to see, how to use it.

If you feel a post has answered your question, please click on " Best Answer ".

K

krushna_moukthikAuthor

Associate III

Hi,

I am currently working on configuring the ADC on the STM32G4 microcontroller, and I’ve encountered an issue where the observed sampling rate significantly differs from the expected values based on the calculations and settings. I am seeking reasons for this discrepancy and guidance to resolve it. I just want to know what error I have done in the following settings.

Observations:
- Observed sampling rate: 171.6 kHz.
- Expected sampling rate based on calculation: 1.7 MHz [(170/4) MHz / (12.5 + 12.5 conversion cycles))
Verified the system clock:
- Used the MCO pin to output the main clock signal and confirmed the CPU is running at the expected frequency.
Reviewed the ADC clock settings:
- Ensured that the ADC module is receiving the configured clock frequency.(sampling time)
Cross-referenced the ADC calculation formula:
- Speed = ADC clock / (sampling cycles + conversion cycles).
- For a 30 MHz clock and 12.5 sampling cycles, the expected rate aligns with 1.75 MHz.

Here's the code i have written

/* USER CODE BEGIN 2 */

HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);

HAL_ADC_Start_IT(&hadc1);

HAL_ADC_Stop_IT(&hadc1);

/* USER CODE END 2 */

/* USER CODE BEGIN 4 */

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {

HAL_ADC_GetValue(&hadc1); // Read the ADC value

HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_1); // Toggle GPIO for timing (PA1)

}

/* USER CODE END 4 */

AScha.3

Super User

Hi,

Seems you are not thinking about the time the CPU needs to do something: starting the ADC with an HAL call might need a microsecond or so, callback from an interrupt also, then add the time for your instructions there, and you see: impossible to get MHz speed for all this together.

So check it with a ADC speed of 10 kHz or lower, to see it working.

And If you want MHz speed, use the DMA to read a block of data at any speed, the ADC can do. This is the only way to get high speed conversion to the ram.

Or doing something else at high speed - data in or out- , the DMA is your friend .

If you feel a post has answered your question, please click on " Best Answer ".

K

krushna_moukthikAuthor

Associate III

I agree that theoretical calculation may be wrong!.

Now as you the waveforms GPIO in the interrupt is toggling at the 142,8Khz attached image.

System clock is 170Mhz

Mode: IN1 Single Ended
Clock Prescaler: Synchronous Clock Mode Divided by 4
Resolution: 12 bits
Data Alignment: Right
Continuous Conversion Mode: Enabled
Sample Time: 2.5 Cycles

please help in understanding how I got this 142.8Khz

AScha.3

Super User

>please help in understanding how I got this 142.8Khz

Well, i cannot know, what you doing...

so at first check, is your system running at xx speed : use MCO pin, set it to main clk /10 , or whatever, and look with a scope on MCO then; just to verify ,your cpu is running that speed, you expect .

Then look at ADC clock: what you set , going to ADC module ?

Then check, whats you do with ADC (read in manual...) , set to the mode (group conversion, single conversion etc.);

and the sampling time you set (dont use 2.5 , except your source is very low impedance; set 6.5 or 12.5 ).

-> calculate speed from ADC clock (/ divider) (/ sampling_time + 12.5 conversion_time) -> maybe:

-> 30MHz / 25 = 1.2 MHz . check it with your bit toggling.

If you feel a post has answered your question, please click on " Best Answer ".

K

krushna_moukthikAuthor

Associate III

please share me the app note links or forum links.

Thanks

AScha.3

Super User

app notes ...see at STM :

ed. ->

https://www.st.com/en/microcontrollers-microprocessors/stm32g431rb.html#documentation

+ for forum links : you can try search function yourself ...

If you feel a post has answered your question, please click on " Best Answer ".

I

Imen.D

ST Technical Moderator

Hello @krushna_moukthik ,

Ensure that the ADC is properly calibrated, this helps reduce offset, gain errors and can affect the accuracy of the sampling rate.

You can refer to these application notes:

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks

B

BitCurious

Associate II

Hello
I am also facing the same issue in the same board :D , my code looks like

while (1)
{
HAL_ADC_Start_IT(&hadc1);
HAL_GPIO_WritePin(PA9_GPIO_Port, PA9_Pin, GPIO_PIN_SET);
}

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
HAL_GPIO_WritePin(PA9_GPIO_Port, PA9_Pin, GPIO_PIN_RESET);
adcBuffer = HAL_ADC_GetValue(&hadc1);
}

ADC : 12 bit, single ended, 60Mhz(sychronous), ADC1 - IN1, 2.5 cycles sampling time, Fast channel

theoretically, it should be 250ns, but i am getti ng 2590ns pollADC60mhy2.5cyclesnodelay.jpg

AScha.3

Super User

So please open a new thread with your question, not capture others ...

If you feel a post has answered your question, please click on " Best Answer ".

MasterT

Lead II

First, you've missed :

Sampling Rate=fADC /{ [sampling time(in cycles)] + [resolution (in bits)] +(0.5)}
Substituting the values:
Sampling Rate=(170 MHz /ADC Prescaler: Synchronous Clock Mode Divided by 4)/ (2.4+12+0.5) ≈ ~~11.33 MHz~~

Second don't use interrupt , better way to verify sampling is to set array for adc samples and feed pwm with known frequency (confirmed with o-scope) to adc input.

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