I am using HSI as a system clock and PLLSAI1R ADC clock.With PLL, ADC1 clock value becomes 80 MHz.I am using End of conversion interrupt in continuous conversion mode on the channel 5.How can I measure sampling rate of the ADC,?

HelloI need to design an EFT filtering circuitry in front of the DC-DC power lines to suppress industrial transients, according to standart IEC 61000-4-4.I need performance criteria A (device is not affected any of the transients) suppression for at ...