Help Understanding/Navigating STM32H7 RM, DS, and ADC Getting started

[zirogravity]

Hello,

I am working with:

1. NUCLEO-H745ZI-Q => STM32H745ZI-QZIT6U => 144-LQFP
2. RM0399 Rev 4
3. DS12923 Rev 2
4. AN 5354 (Getting started with the STM32H7 Series MCU 16-bit ADC)

According to DS12923 Rev Table 96 note 3 is that Table 96 values:

"These values are valid for UFBGA176+25 and one ADC. Refer to Getting started with the STM32H7 Series MCU 16-bit ADC (AN5354) for values of other packages and multiple ADCs operation.

but:

According to AN5354 Tables, 14, 15 and 18 LQFP144 Direct and Fast Channels at 16 bit resolution have max data rates of 1.2, 1, 0.7, MSps for single, dual and triple ADC respectively. No mention of Slow Channel max data rates? I am currently using slow channels since fast/direct channels are limited.

According to RM0399 Rev 4 section 26.4.13 the sampling time values may be selected as SMP=N*ADC clock cycles. If I attempt the "arithmetic", unless I am not following something correctly of course, I cannot seem to back out the values of Table 96 DS12923 Rev 2. For example:

fADC=10MHz SMP=1.5 Max MSps = 1. How?

Table 12 suggest that for LQFP144 Maximum ADC frequency is 12MHz. So I am trying to calculate allowable sample time i.e. SMP= N*ADC but I cannot seem to sanity check my values even with the given values of the STM provided table.

I have been learning about the ADC and I believe I am overrunning the ADC because I have the wrong clock and SMP set. I also think I accidentally stumbled on AUTDLY which is making things "work". Please consider seeing my schizophrenic post where this all started.

[TDK]

Edit: deleted some stuff.

It may be easier to work the other way. What sample rate, channel count, accuracy, etc are you looking for? If it's simply the highest single channel rate, you should be able to find a clock setting that can produce that without much trouble.

[MasterT]

Q: fADC=10MHz SMP=1.5 Max MSps = 1. How?

In DS page 184 there is a formula "arithmetic":

Total conversion time (including sampling time) Resolution = N bits - - ts + 0.5 + N/2 - - 1/fADC

1.5 + 0.5 + 16/2 = 10 clocks, means at 10 MHz ADC's clock, conversion time equals to 1 MHz or 1 MSPS.

[zirogravity]

Thanks @MasterT. This is very helpful. I was using Tcon=Sampling Time + 7.5 ADC Clock Cycles on page 972 of the RM. I will compare the two but at first glance they look different. 

[zirogravity]

@TDK

I am in a kind of exploratory and/or evaluation of the part limits and I do not yet have hard requirements.

The current approach I have assumed is to examine the part "specification limits" per the part documents:

• For 16 bit resolution, LQFP144 = 15 slow channels per AN5354 Table 8
• Max ADC frequencies and Max sample rates seem to be specified for the Direct and Fast channels per AN5354 Table 12 and per AN5354 Tables 14, 16, 18 but not for Slow Channels.
  
  • 1 x ADC(12MHz), 2 x ADC(10MHz), 3 x ADC(7MHz)
  • 1 x ADC(1.2Msps), 2 x ADC(1Msps), 3 x ADC(0.7Msps)

Based on these specs I arrive with the idea that:

• For slow channels the performance is likely less than 1.2Msps, 1Msps ,and 0.7Msps i.e. those of fast/direct channels depending on the number of operational ADCs on/off

The limits I am hoping to calculate (test eventually) would be as follows:

1. Using all 15 slow channels at 16 bit
2. Conditionally turning ADCs 1, 2, 3 on/off during different operational measurement needs

How would one calculate the max sample rate during the operation of 1 x ADC ,  2 x ADC, 3 x ADC, at 16 bit resolution for the slow channels similar to the tables ST provides?

[MasterT]

On page 972 they are talking 14-bits resolution, I referred to 16-bits. You can estimate for lower resolution Tsampl + 0,5 + N/2, like Tsampl + 4.5 for 8-bits

[zirogravity]

@MasterTThanks again! I really appreciate it. I did not catch that the 7.5ADC Clock cycles was specific to 14 bit. I thought 14 bit was just specific to the example section of page 972 i.e. I thought the equation before the example was for the "general case" if a clock had been selected. I had been using that for days banging my head against the bits :) I see now that the table equation is the general case.

[MasterT · Accepted solution]

Q: 

How would one calculate the max sample rate during the operation of 1 x ADC ,  2 x ADC, 3 x ADC, at 16 bit resolution for the slow channels similar to the tables ST provides?

A:

Since max ADC frequency provided in table 12, than

1. Calculate  T-sampl based on DS table 97, 1.72E-07 or

	T sampl	N-bits	F-adc, MHz	Period	k
1	1.72E-07	16	12	8.33333333333333E-08	2.064
2	1.72E-07	16	10	0.0000001	1.72
3	1.72E-07	16	7	1.42857142857143E-07	1.204

than T-conversion = k (rounded up) + 8.5 = 11 for 1 or 2 adc, and 10 for 3-adc. 

Rate-1 = 12 / 11, 

Rate-2 = 10 / 11,

Rate-3 =  7 / 10,

[zirogravity]

Thank you @MasterT for your time and very helpful write up.

[MasterT]

I tested my nucleo-H743zi2,  never get more than 12-bits, 4 last out of 16 just noise. I blamed a package, since F-adc, T-sampl, calibration linearity/ offset makes no difference. 

Also app note from ST doesn't provide a circuits - driver of the adc. To get 16-bits noise-free a lot depends on driver and a reference voltage. Nucleo has an option to cut Vcc & V-ref to apply external, so I tried w/o any improvement