FDCAN STM32H753VIT6 – Unable to Achieve >1.92 Mbps Data Rate (PLL1Q = 40 MHz)

[pavanl]

Hi ST Community,

I’m working on a CAN FD project using the STM32H753VIT6 and facing a limitation with data phase bitrate while using Bit Rate Switching (BRS).

My Setup:

• Controller: STM32H753VIT6

• FDCAN clock source: PLL1Q

• PLL1Q output: 40 MHz

• Frame format: CAN FD with BRS (FDCAN_FRAME_FD_BRS)

• Nominal (arbitration) bitrate: 1 Mbps

• Target data bitrate: 2 Mbps or higher
  
  

   Problem:

  Despite the configuration, I'm not able to achieve more than ~1.92 Mbps on the data phase. Even when I reduce the number of time quanta or adjust prescalers, the speed does not increase beyond this limit.

   My Questions:

  1. Is there any known limitation when using PLL1Q = 40 MHz for FDCAN clock?

  2. Is the STM32H753 internal FDCAN limited to certain bitrates per kernel clock frequency?

  3. Could internal synchronization or sampling constraints prevent achieving the expected 2.5 Mbps from a 40 MHz FDCAN clock?

     Attachments:

     • main.c file

     • Oscilloscope screenshot showing BRS waveform and time base

     • STM32CubeMX clock configuration screenshot

  Any insights or suggestions would be greatly appreciated!
  
  Thanks in advance,
  Pavan

[mƎALLEm]

Hello,

I don't think there is a limitation 40Mhz vs bitrate > 2Mb/s

Refer to this article: STM32 FDCAN running at 8 Mb/s on NUCLEO boards on which we showed that we can reach 8Mb/s in data phase.

Check also your transceiver bandwidth.

Meanwhile refer to this article: FAQ: Fixing STM32 FDCAN communication disruptions - APB bus, kernel, and time quanta clocks and check if you are in the same situation

[pavanl]

Thank you for your response.

My transceiver bandwidth is 5 MHz for FDCAN and 1 MHz for classic CAN.

I followed the same clock configuration as mentioned, but I'm still unable to achieve a speed beyond 2 Mbps. Could you please suggest the best approach to troubleshoot this issue? If there’s a possibility of any mistake in my configuration or code, I would really appreciate your guidance.

Thanks again.

[mƎALLEm]

Were you able to achieve the target bitrate in Loopback mode?

[pavanl]

No, I did not measure the actual bitrate during the external loopback test. I used that mode only to verify the basic communication functionality. Without confirming the exact timing parameters, I proceeded to normal mode, where I am currently testing the communication between two transceivers on the same STM32H753 device. Specifically, I am transmitting from FDCAN1 and receiving on FDCAN2, and then vice versa.

My primary goal is to evaluate the maximum achievable data rate in a real physical setup using CAN FD with Bit Rate Switching (BRS). I have configured PLL1Q at 50 MHz (the max supported for FDCAN on this device), and I am using 64-byte payloads with proper timing configurations.

Could you please guide me on:

• The best practices for achieving and validating the maximumFDCAN speed on STM32H7?

• How to accurately measure and verify the bitrate during transmission.

[mƎALLEm]

Please test the loopback mode before to proceed ..

[pavanl]

Sure, I will test the loopback mode before proceeding. Just to confirm, which loopback mode would be more suitable in my case — internal loopback or external loopback?

[mƎALLEm]

External loopback with the same clock and CAN configs and probe CAN_Tx