Introduction
Many customers requested to have FDCAN communicating at 8 Mb/s. We provide a GitHub hotspot that contains a simple project on several STM32 part numbers. The project allows for FDCAN to reach a bit rate of 8 Mb/s in the data phase.
The boards used and tested are:
- NUCLEO-G0B1RE (STM32G0B1RE)
- NUCLEO-G474RE (STM32G474RE)
- NUCLEO-H563ZI (STM32H563ZI)
- NUCLEO-H753ZI (STM32H753ZI)
- NUCLEO-L552ZE-Q (STM32L552ZExxQ)
- NUCLEO-U575ZI-Q (STM32U575ZIxxQ)
The goal of this article and the examples attached is to prove that STM32 featuring FDCAN peripheral can reach 8 Mb/s. Other timings consideration such as SJW, transceiver delay compensation etc., are not the subject of this article.
1. FDCAN clock configuration
FDCAN communication needs the usage of an accurate clock source such as a crystal. NUCLEO boards were used to run FDCAN @ 8 Mb/s example. Since most of the used NUCLEO boards do not have a crystal connected to the target MCU HSE pins, STLINK MCO output is used in this case with HSE in bypass mode.
Some NUCLEO boards have STLINK/V2 while others have STLINK/V3 (see figure 1 below). For the STLINK/V2 boards, the STLINK MCO output clock is generated from the external Crystal connected to the MCU managing the STLINK/V2 (STM32F103 MCU) generating 8MHz.
For the STLINK/V3 boards, the MCO is configurable and the default clock source is generated from HSI/2 = 8 MHz (managed by the STM32F723 MCU) which is not recommended in CAN communication. In this case, we need to modify the STLINK-V3 MCO output frequency using STM32CubeProgrammer or STLINK firmware upgrade tools. Refer to this article on how to use STLINK-V3 MCO output on NUCLEO boards as a precise clock source for STM32.
Figure 1. Nucleo STLINK modules
To run the examples correctly, you need first to check if the NUCLEO is having ST-LINK/V2 or V3 version to set the correct frequency value for HSE.
Table 1 summarizes the HSE configuration, the system clock config as well as the FDCAN clock value.
Table 1. Boards HSE source summary
|
Board |
HSE frequency value (MHz) |
FDCAN clock (MHz) |
|
NUCLEO-G0B1 |
8 (STLINK/V2 MCO) |
64 (PCLK) |
|
NUCLEO-G474 |
24 (Crystal available) |
160 (PLLQ) |
|
NUCLEO-H563 |
6 (STLINK/V3 MCO) |
192 |
|
NUCLEO-H753 |
5 (STLINK/V3 MCO) |
120 |
|
NUCLEO-L552 |
8 (STLINK/V3 MCO) |
104 |
|
NUCLEO-U575 |
5 (STLINK/V2 MCO) |
160 |
2. FDCAN bit time configuration
The CAN FD frame has two bitrates on each phase: arbitration phase and data phase (See figure 2).
Figure 2. CAN FD frame and the different phases
Source for figure 2:
Hartwich, F. (2013). Bit Time Requirements for CAN FD. Robert Bosch GmbH.
Retrieved from https://www.bosch-semiconductors.com/media/ip_modules/pdf_2/papers/icc14_2013_paper_hartwich_1.pdf
In the arbitration phase, nominal bitrate is used, while in the data phase, data bitrate is used.
In this section, we provide FDCAN timing computation for both bitrates. It is based on a given platform and inspired from the Cube HAL example provided for H5 here. The bitrates that are considered are:
Nominal bitrate = 1 Mb/s
Data bitrate = 8 Mb/s
In the provided examples, the FDCAN clock frequency value is chosen in such a way to have a multiple of 8. This to ensure we can get adequate dividers to get 8 Mb/s for the data phase.
The CAN bit time is the inverse of the bitrate: bitrate = 1 / bit time. The bit time is the sum of three components like shown in the figure 3.
Source for figure 3: AN5348, Rev 4: Introduction to FDCAN peripherals for STM32 MCUs.
CAN bit time is the sum of different segments:
CAN bit time = tSyncSeg + tBS1 + tBS2
Where:
tSyncSeg = 1 tq (fixed)
tBS1: Bit time segment 1 = DataTimeSeg1 (in Cube HAL)
tBS2: Bit time segment 2 = DataTimeSeg2 (in Cube HAL)
FDCAN bitrate in the two phases (arbitration and data) is computed as the following:
The time quanta tq is generated from the FDCAN clock with a prescaler:
So, in the final FDCAN bitrate formula is as follows:
Let us take an example of STM32H753ZI MCU (NUCLEO-H753):
2.1. Data bit time settings at 8 Mb/s
If we fix DataPrescaler (parameter in FDCAN HAL) to the minimum prescaler we can have, that is, to the value 1, FDCAN Data bitrate is:
We need that fdcan_ker_clk value to be a multiple of 8 to get 8 Mb/s.
120 MHz is dividable by 8 => 120 MHz / 8 = 15 MHz.
=> tSyncSeg + tDataTimeSeg1 + tDataTimeSeg2 = 15 x tq
=> SyncSeg + DataTimeSeg1 + DataTimeSeg2 = 15
Setting the sample point at ~60% for data phase:
SyncSeg + DataTimeSeg1 = 60% of the bit time = 15 x 60 / 100 = 9
=> DataTimeSeg1 = 9 - SyncSeg = 8.
Note if the value is not an integer we round it to the nearest integer value.
=> DataTimeSeg2 = Bit time - DataTimeSeg1 - SyncSeg = 15 - 8 - 1 = 6
To get 1 Mb/s in the arbitration phase at 120MHz of FDCAN kernel clock (fdcan_ker_clk):(
=> SyncSeg + NominalTimeSeg1 + NominalDataTimeSeg2 = 120.
Setting the sample point at ~85% for data phase:
SyncSeg + DataTimeSeg1 = 85% of bit time = 120 x 85 / 100 = 102. If the value is not an integer, we round it to the nearest integer value.
=> DataTimeSeg1 = 102 - SyncSeg = 101.
=> DataTimeSeg2 = Bit time - DataTimeSeg1 - SyncSeg = 120 - 101 - 1 = 18
Table 3. Nominal phase bit timing to be used
| NominalTimeSeg1 | NominalTimeSeg2 |
| 101 | 18 |
3. Hardware setup
A basic CAN bus structure needs to be used to run the examples (figure 4). Two nodes are connected to the CAN bus with FDCAN transceivers.
Figure 4. CAN bus structure used with the example
The transceiver that has been used to run the FDCAN examples at 8 Mb/s is the MCP2562FD. It supports a CAN communication bitrate up to 8 Mb/s (see figure 5 for the hardware used). Note that if the transceiver does not support the communication bitrate to be used, the communication fails. So, please ensure to use the adequate FDCAN transceiver and refer to the transceiver datasheet.
Two terminating resistors of 120 ohm are connected on both ends of the bus.
The examples have been tested using two meters of twisted-pair wires.
Figure 5. Transceiver schematics using the MCP2562FD
