FAQ: Fixing STM32 FDCAN communication disruptions - APB bus, kernel, and time quanta clocks

Christophe VRIGNAUD · ‎2024-10-22

Introduction

This article dives into how you can avoid communication disruptions. In some cases, you may see that FDCAN messages are repeated even though they’re acknowledged. You may also observe some other unexpected behavior. We cover a possible cause of the issue and how to solve it.

1. Complying with the relation between the clocks

When a communication issue appears, a possible cause can be the noncompliance to the following rule shown below.

The FDCAN requires that the CAN time quanta clock is always below or equal to the APB clock.

fdcan_tq_ck < fdcan_pclk

2. Clocks applied to the FDCAN peripheral

Two clocks are applied to the FDCAN peripheral as shown on the following table extract from the reference manual of STM32H5 (RM0481).

2024-10-11 16_32_14-STM32H523_33xx, STM32H562_63xx, and STM32H573xx Arm_Sup_®__Sup_-based 32-bit MCU.png

The kernel clock directs to the FDCAN core, which manages the CAN protocol, the communication lines, and the baud rate.

The APB clock allows configuration and control of the FDCAN subsystem through registers, and also to access the message RAM.

3. FDCAN subsystem block diagram

STM32H7 (except STM32H7RS)	STM32L5, STM32U5, STM32G0, STM32G4, STM32H5, STM32H7RS

The two block diagrams above are extracts respectively of the reference manual of STM32H72x/3x (RM0468) and of the reference manual of the STM32G4 (RM0440).

They display both 3 FDCAN units and a common block on the top. The clock domains, APB and kernel, are displayed with different colors: light and dark gray, or light yellow and gray.

The FDCAN peripheral is connected to the APB1 peripheral bus (refer to the MCU block diagram in the datasheet, generally figure 1). In STM32CubeMX, the FDCAN peripheral clock fdcan_pclk is the APB1 peripheral bus clock as shown in the image below.

2024-10-11 14_23_32-Clipboard_modified.png

The kernel clock fdcan_ker_ck is delivered through a multiplexer allowing to choose among several sources.

2024-10-11 15_02_00-STM32CubeMX Untitled__ STM32H725ZGTx.png

4. FDCAN time quanta clock

The FDCAN cores are clocked by a common FDCAN time quanta clock fdcan_tq_ck that is used to define the baud rate of the communication channel.

As shown on the block diagram, this clock is generated from the kernel clock as follows:

fdcan_tq-ck = fdcan_ker_ck / DIV

Depending on the STM32 series, the divider is defined by the CDIV[0..3] bits in the FDCAN_CCU_CCFG register (STM32H7) or by the PDIV[0..3] bits in the FDCAN_CKDIV register (for other STM32 series).

The value by default is DIV = 1. When necessary, the divider can be modified to comply with the rule given above between the time quanta clock and the APB clock (fdcan_tq_ck < fdcan_pclk).

The table below summarizes the conditions applying to DIV.

STM32H7 (except STM32H7RS)	STM32L5, STM32U5, STM32G0, STM32G4, STM32H5, STM32H7RS


DIV in [1..30]	DIV in [1..30]
------- The CCU (clock calibration unit) is common to all FDCAN units. ------- Only FDCAN1 has access to CCU registers. ------- IF CCU is bypassed The DIV is set at initialization by the application to fulfill the CAN time quanta clock requirement. ------- IF CCU is enabled The DIV is managed by the CCU Baud rate prescalers Prescaler = 0 (nominal and data prescalers for all the FDCAN units) Kernel clock fdcan_ker_ck > 80 MHz FDCAN bitrates Nominal bitrate < 1 Mbit/s Nominal bitrate < data bitrate < 8 Mbit/s	------- The configuration is common to all FDCAN units. ------- Only FDCAN1 has access to the CKDIV register. ------- The DIV is set at initialization by the application to fulfill the CAN time quanta clock requirement.

Conclusion