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Data coherency with DMA and I2S audio on STM32H7

Alefal
Associate II

Moving from a audio effect prototype based on the STM32F407 to the STM32H757. Did a lot of stuff on the F4 with audio but on the H7 I'm getting stuck and can't get a simple audio loopback with DMA.

I'm using Cirrus Logic's CS5343 and CS4344 as external ADC/DAC connected to the I2S interface. I2S data frames are read and written in memory with DMA configured in circular RX/TX mode

.

Without DMA, audio loopback is OK. However, with DMA, the RX buffer isn't filled. The half complete and complete callbacks are triggered tho.

I'm aware that DMA can't access DTCM RAM and that with cache enabled, data coherency should be taken care of thanks to the MPU configuration and modification of the linker script :

MPU creates a region of 128kB device memory type (TEX : 0b000, not cacheable, bufferable, shareable)

RX and TX buffers (8kB each) subsections have been placed at 0x30010000 and 0x30012000 (SRAM1 in D2) in the linker script.

I tried to move the buffers in other RAM domains, make the MPU Region as shareable normal memory type but my Rx Buffer remains empty and/or doesn't update.

What I don't get is why my rx buffer isn't filled and updated by the DMA in the first place. If anyone got any clue or hints about what I'm missing, I'm all ears.

You'll find my whole main.c file attached.

And here's the modification of the linker script I've done :

.buffers(NOLOAD) :

{

. = ALIGN(4);

. = ABSOLUTE (0x30010000);

*(.rxBuffer)

. = ABSOLUTE (0x30012000);

*(.txBuffer)

} >RAM_D2

18 REPLIES 18
Alefal
Associate II

>  in case you are using HAL stuff, sometimes there's one or the other peripheral's DMA or interrupt enable missing. Checked that?

Yes, my halfcplt and cplt callbacks are fired, so DMA's interrupts look fine

LCE
Principal

Maybe using 24 bit in I2S peripheral and half-word in DMA is not such a good idea?

In your I2S2_Init:

 hi2s2.Init.DataFormat = I2S_DATAFORMAT_24B;

DMA init:

hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

I have both I2S and DMA set to 32 bit , that's working here on H723 / H735.

Piranha
Chief II

Also on this MCU one should use SAI peripheral, which is much more flexible and easier to use, compared to SPI/I2S peripheral.

Alefal
Associate II

Thanks a lot for your answers, LCE pointed me in the right direction, using DMA_P/MDATAALIGN_WORD solved the issue !

Still a bit confused about why it worked with halfword on the F4 tho.

Thanks for coming back with the solution.

> Still a bit confused about why it worked with halfword on the F4 tho.

The SPI/I2S unit in 'F4 is essentially a 16-bit peripheral.

Why halfword does not work (an by that I mean probably returns zeros?) on 'H7 is IMO a bigger mystery. The 'H7 SPI/I2S is a reworked unit and is a beast. It's hard to please a beast.

JW

PS. Please select LCE's post as Best so that thread is marked as solved.

Oh, it's in the fine-print, indeed:


_legacyfs_online_stmicro_images_0693W00000biJezQAE.pngJW

STM32H757's reference manual is RM0399 (screenshot comes from RM0468).

Seems like they should add this line to the RM0399 too.

Humm, what a lucky choice of RM to find such a particular remark... 

Current RM0399 is rev.3 dated 27-Feb-2020, the remark probably appeared in some of the later revisions of RM0468 i.e. in 2021. All these while deeply in The Big Parts Shortage, so probably nobody complained yet. I guess a newer revision of RM0399 will contain it, but who knows when will such revision appear.

It's not uncommon that for newer informations or even errata you have to browse through other RMs, ST does not issue updated RM/ES regularly.

JW

[EDIT]

😉
_legacyfs_online_stmicro_images_0693W00000biKwaQAE.png

Oh okay, thanks a lot for your help and your time!