10 msps dac and adc stm32 recommendation

[Seren200018]

Dear Stm32 users,

I currently plan to design an analog function generator and capture System.
The old System used an analog lock in amplifier circuit to excite and capture noisy signals from a measurement source.

For cost and pcb size saving i am considering to switch to a software Version as i can speed up the measurement by using a multisine instead of a swept sine. The frequency range is 10kHz to 1Mhz. A good Resolution is around 1k to 2k Points per decade.

My current plan would be using a function generator with variable frequency to trigger the internal dac and adc at up to 10 MHz. Both using ring buffers. The captured data is stored in an external psram chip for later Analysis. The storage qspi transfer is triggered at half point of euch conversion.

Do you think this is feasable? What do you think would be a viable ic? STM32L4?

P.s.A Sampling rate of a maximum of 10MSPS should suffice.
According to [AN4566](https://www.st.com/content/ccc/resource/technical/document/application_note/6f/35/61/e9/8a/28/48/8c/DM00129215.pdf/files/DM00129215.pdf/jcr:content/translations/en.DM00129215.pdfcs-1.pdf) the maximum Performance of the DAC of L4 is 10MSPS and of L4+ 12MSPS.
The L4 has a maximum ADC Frequency of 5.3 MSPS. I thought about using dual alternating trigger mode. If necessary, I can feed the signal to multiple channels and pins.

My current biggest concern are the DMA channels, as both ADC and the DAC need DMA channels as well as any additional memory chip.

Best regards,
Seren

[MasterT]

How many samples/ big array is?

Definitely, complexity 'd be greatly reduced if only internal memory in use.

And what kind of analysis/ processing data considered?

 I recently tested adc performance of nucleo-G474re, and find out that adc is stable in case of high overclocking, about x3 times. Sampling rate gets to 11.8 MSPS (168 MHz clock), with only slight deterioration in ENOB down to 6-bits.

ADC's internal S/H is quite good for under-sampling technics, here is SNR of 20 MHz sine wave.

[Seren200018]

I think the internal memory can be enough. I calculated that I roughly need 1.6ksps at max for DAC and ADC respectively. 6 bits is quite low. 8 to 10 would be far better, and 12 would be near optimal.

With some trickery I can oversample by hand by combining multiple measurement windows but, I am worried that this might slow down the whole measurement to a crawl as it would take a lot of additions and even by using bitshifting instead of division it might be slow.

[MasterT]

My estimation in 6-bits is very unprecise, didn't account for noise in very wide bandwidth >20MHz.

Posted picture shows fft results calculated on the same dut (g474re), board also updates 480x320 tft screen.

I have tested averaged data by accumulating array over a few cycles, uCPU is fast but not enough to process fft at 11.8MHz.

summ & shift 1 clock cycles, float div with FPU about 15-18 depends on loading data.