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​@Erwan SZYMANSKI, we are about to design a new hardware based on MP2.Is REV Y ETH1 port stable when used in RGMII mode?Is this config recommended?ETH1 in RGMII mode and ETH2 in RMII

This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.Is there a function to get the currently set ID in the SVGImage widget?

Environment: TouchGFX 4.26.0, Windows, Ruby 3.0 (bundled MinGW env). Text database: texts.xml is 13.7 MB - 20 languages x 8,255 text entries = 165,100 translations. "remap": "yes" in application.config, binary translations and binary fonts both enabled for one of the passes. Symptom: make texts took ~181s cold on a developer machine, ~2min on our build server. Adding timing markers around each phase of Generator#run put 146s of it inside StringCollector#run. Cause: the fold that collects the translations, in framework/tools/textconvert/lib/string_collector.rb:    all_strings = Array.new(languages.count, Array.new)    text_entries.each do |text_entry|      text_entry.translations.each_with_index do |translation, lang_index|        all_strings[remap_global ? 0 : lang_index] += [translation]      end    end`a += [x]` allocates a new array and copies the whole accumulated contents on every iteration, so this is O(n^2) in the number of translations. With global remapping every language fold

TouchGFX 4.26.0Low severity bug. Only visual in Designer. In the generated code the correct alignment is used.Steps to reproduce:create TextArea. Disable “auto-size” Set textID with text element that has right alignment. The shown alignment is still left aligned.When Designer is restarted, the correct alignment is shown again.

TouchGFX version: 4.26.0Visual Studio version: 18.6.3When TouchGFX generates or updates the “TouchGFX/simulator/msvs/Application.vcxproj” file it creates lines with<ClCompile Include="path/to/some/file.cpp"/>but Visual Studio updates the lines to <ClCompile Include="path/to/some/file.cpp" />. Notice the extra space. This means that in version control sometimes commits will be added without the space and sometimes with the space. This overcomplicates merges and causes merge requests. Please update the XML library or fix the output to be consistent with Visual Studio.

This is a small feature request to fix an annoying quirk of the TouchGFX Designer.When opening the texts menu in the designer, all of the texts groups are expanded by default. In projects with many texts/groups, its tedious to collapse all of the groups or scroll to the bottom of the expanded groups. I think it would be better if either TGFX stored the state of the groups expansion OR collapsed them all by default.

The problem described in https://community.st.com/stm32-mcus-touchgfx-and-gui-33/duplicit-include-paths-are-added-to-keil-project-when-touchgfx-project-is-regenerated-151799 ist still there. The topic was closed a year ago and it seems that nothing happened since then.Please provide a solution!

I have an STM32WB05 board (approx 30mm x 30mm) with the following major components :STM32WB05KZV6TR, LTC4095EDC, LTC3531ES6-3.3, LSM6DSV80XTRI have followed the reference design for running on SMPS.When running directly from VDD (3.3V) it works great. Advertising, connecting reliably.When running through the BuckBoost it does not advertise (with either a LiPo feeding or a bench PSU at 4V or via the USB charging circuit) . No errors, no obvious issues.. just cant see or connect to it over BLE.  I checked that TX_SEQUENCE was active and it is. Registers look the same for both modes. VDD does have some noise but it is within spec for the LTC3531 in burst mode. I purchased a TinySA Ultra+ and have taken traces. I can see the advertising (attached)Really need to help to diagnose.. is it a lost cause having the BuckBoost on a board this small?Let me know how to configure the TinySA also for more detailed traces as i am struggling (so is Claude!) 

Hi all,I'm stuck on debugging with the STM32N6570-DK and could use some help. I've spent a few days on it and I'm running out of ideas.My setup:- Board: STM32N6570-DK (Rev B, device ID 0x486)- STM32CubeIDE 2.2.0 (ST-LINK GDB server 7.14.0)- STM32CubeProgrammer 2.23.0- ST-LINK FW: V3J17M11- CubeN6 FW package V1.4.1- Project made in CubeMX with FSBL + Appli (Appli runs from external flash)- Boot switches set for dev boot (BOOT1 = 1)What's happening:Most of the time the debug session doesn't even start. I get:"Target unknown error 32Error in initializing ST-LINK device.Reason: Unknown. Please check power and cabling to target."Sometimes it does connect. When I launch the Appli debug config, it programs the Appli into external flash fine (I can see it erasing sectors and downloading), but then it stops with "Setup exceptions" and the core is sitting at 0x18003a1a (boot ROM area, no source).When I launch the FSBL debug config (with the Appli .elf added in the Startup tab), the GDB server co

Heyho,next G4 problem…G431 with an audio ADC (TI’s PCM1822) connected to SAI1_Block_A, SAI is in master receiver mode, meaning it provides the I2S clocks for the external ADC.DMA is used, circular, 32-bit.Signals looking good at all audio sampling frequencies, up to 192 kHz.Problem:always at 1st start, and every now and then after a SAI + DMA stop and restart, somehow the 2 ADC channels are swapped.I checked all I2S signals with a scope, and data is always where it’s supposed to be.I can check the DMA buffer, it’s definitely the SAI.BAD buffer / channels swapped, signal connected to RIGHT ( = R ) channel only,so LEFT should be 0 L R L R L R L R000: +0.31 -0.00 +0.37 +0.00 +0.38 -0.00 +0.36 -0.00008: +0.30 -0.00 +0.20 -0.00 +0.09 -0.00 -0.04 -0.00GOOD buffer: L = 0, R = signal L R L R L R L R000: +0.00 +0.26 +0.00 +0.16 +0.00 +0.04 -0.00 -0.09008: +0.00 -0.20 -0.00 -0.30 -0.00 -0.36 +0.00 -0.38our analyzer: Here are the D

Hi,I am trying to understand the temporal structure of a single VL53L9CX depth-map acquisition for measurements of moving objects.From UM3683 and the register documentation, I understand that a frame is produced using 6 or 7 ranging steps, with successive channel illuminations within those steps.I have a few questions: Are all 54 × 42 spatial zones effectively observed over the same sequence of ranging steps, or are different zones/groups of zones acquired at different times within a frame? If there is any spatially varying acquisition timing, is the mapping from zone (row, column) to acquisition step/channel deterministic and documented? Is the timing of each ranging step and Channel 0/1 illumination deterministic relative to an external SYNC_IN trigger? If so, is there documentation giving these offsets or enough information to calculate them from the configured number of shots/blanking periods? Are intermediate 54 × 42 measurements available after individual ranging steps or c

Hi, I’m trying to use a VL53L9 with a microcontroller which have 128kB of RAM. For this I use the STM32CubeExpansion_53L9A1_V1.0.0 package. The problem is the streaming library delivered within the package is not made for low RAM usage. It’s stack usage is high. Too high for the microcontroller I use.Is there VL53L9 software implementation available for low RAM usage ? Regards,Nicolas

Described below method is intended to perform correction of the static ADC’s non-linearity in software using LUT. It requires pure sine-wave source only, that can be generated by any available analog circuitry. Basically, it corrects non linearity induced by signal conversion analog front end all together, that includes ADC and it’s drivers, signal conditioning / amplification stages, inputs protection, etc. There is a way to do the same linearity correction by applying linear ramp voltage and generating error LUT table. New method is using sine-wave, and consequently has a few advantages over “classic” : 1. Linearity of the sine-wave is much more easier to verify down to -140 -160dB (0.1 – 0.01 ppm) using simple tween-T notch filter. 2. Analog front end may include DC blocking capacitors. 3. Calibration test signal could function in the “working band” area, and some complex dynamic distortion of the drivers (due to fall of the AOL over frequency, output stage

i have a problem that has bugged me for a while now. Im using a stm32f4 microcontoler to read data from stpm34 microchip, but i can not establish a spi connection betwen them. With my logic analyzer i can see that i send mosi, the clock works and i believe the enable , chipselect and syn all work as they should. But on miso i get 0xffffffff or 0x808080 or 0xffcffeff... changing randomly. I dont know what is causing the problem. Im designing my own pcb but for now im powering the chip via arduino, and i am using stm32f4 discovery(arduino, becase the discovery has only 3v) gnd connected ofcoirse.Is it soldered wrong? Are the pads on the bottom not connected? Is the code not ok?.... any help will be welcomed and thank you in advance. Code: /* USER CODE BEGIN Header */ /** @file : main.c @brief : Main program body @attention STM32F4 + STPM34 SPI FIXED VERSION */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /

Hello everyone,I am working on Ethernet communication using the STM32H750B-DK with STM32CubeIDE and LwIP. I am using the onboard LAN8742 Ethernet PHY and a direct Ethernet connection between the PC and the board. LwIP is configured with NO_SYS = 1, and I am continuously calling MX_LWIP_Process() in the main loop. When I check the Ethernet traffic in Wireshark, the PC continuously sends ARP requests asking for the STM32 MAC address, but the STM32 does not send an ARP reply. While debugging the gnetif structure, I see PHYLinkState = 0, speed = 0, and duplex = 0. I also checked the STM32H750B-DK documentation and found that the onboard Ethernet PHY is connected through MII. My CubeMX project was initially configured for RMII, so I changed the Ethernet configuration to MII. I am also checking the Ethernet DMA/LwIP memory configuration and moved the Ethernet descriptor and RX buffer sections to D2 SRAM using the linker script. However, I still cannot get a ping response from the board.Curre

Hello,The Neural-ART compiler (atonn) crashes with an internal assertion when I run `analyze` on a quantized 1D CNN. The crash happens on the pooling unit and I cannot get past it.EnvironmentST Edge AI Core v2.2.0-20266 (X-CUBE-AI 10.2.0), Windows, via STM32CubeMX Target: stm32n6 Also reproduced on ST Edge AI Developer Cloud with ST Edge AI Core v4.0.1-20581 -> same assertion, so this does not look version-specific.Model Keras model exported to TFLite, full int8 quantization (int8 input and output, per-channel), batch size fixed to 1.Architecture (1D CNN for signal classification):  Input [1, 3000, 1]  3x { Conv1D -> BatchNormalization -> ReLU -> Dropout -> MaxPooling1D(pool=2, stride=2) }     conv filters = 128 (k=30), 32 (k=20), 4 (k=10), padding 'same'  Flatten -> Dense(512) -> BN -> Dense(128) -> Dense(32) -> Dense(4, softmax)Input tensor quantization has a non-zero zero-point (scale ~0.0366, zp -2).When converted, TFLite lowers the model to CONV_2D (x

I am going to build linux system on a board based on STM32MP257F and have read many kinds of related technical documents.In the process, a question bothers me. I want to modify only several components such as uboot and kernel in existing STM32MPU Distribution Package. To do that, the STM32MPU Developer Package is needed because their source cdoes and build tools are required. This is where the major problem lies. Those are as follows:To build the source files, what is used between Developer Package’s SDK and Distribution Package’s BitBake ? After the modified components are built anyway, how and where are their binary images added into the Distribution Package including their configurations ?I have read in the documents that interoperation between the Developer Package and the Distribution one is available.But, I have not found out its actual usage example.

We have a G474 with a 12 MHz oscillator feeding into PF0/OSC_IN and have the device configured in bypass mode. We’re trying to use PF1/OSC_OUT as an ADC input, however we’re seeing a 300mV peak-peak square wave on the pin when our 2 kohm signal is connected to it.Our layout really doesn’t leave enough room for this to be crosstalk, especially since we’re seeing a clean square wave. Is there something internally that could be leaving some clock circuitry connected?For our purposes we can work around the extra noise in software; however, if we do we’d like to ensure that we won’t have any long-term reliability issues from feeding a signal into the clock circuitry.

I was attempting to follow the STM32H563ZI video but I cannot get the current repository for the STM32H5.See Problem1.jpgI want it to upload it but ti comes back with a failureSee Problem2.jpgWhat steps do I need to take to fix this? 

Dear all,I'm implementing Over-the-air firmware updates for a board using the STM32N657 MCU.In the Appli, I download the new firmware binary over Wifi and store it to RAM at a fixed location in AXISRAM5 and 6. In order to flash the new binary to the OctoSPI Flash I prepend a "magic" header to the new firmware binary (still in RAM) and then restart the MCU using `HAL_NVIC_SystemReset`. Then, after this reset the FSBL checks the fixed location in RAM for the "magic" header. If present, it should flash the OctoSPI Flash with the new firmware binary using the ExtMem Manager (I cannot just flash directly from Appli because I use XIP and hence the Appli is running from OctoSPI in memory-mapped mode, preventing writes). I've done similar things with other MCUs and it worked perfectly fine.However, it looks like on the STM32N6, the contents of AXISRAM5 and 6 are not preserved across software resets. At least, checking the "magic" header in FSBL always produces randomly looking results that are

Hello,I am using an STM32H7S3 with STM32CubeH7RS HAL [V1.2.1]. SPI5 drives a display over 3-wire SPI with 9-bit frames (the 9th bit carries D/C).With USE_FULL_ASSERT enabled, HAL_SPI_Init() triggers an assert in stm32h7rsxx_hal_spi.c (line 259 in the current GitHub version):if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)){  assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize));  assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold));}In stm32h7rsxx_hal_spi.h, the macro only accepts 8-bit and 16-bit:#define IS_SPI_LIMITED_DATASIZE(DATASIZE)  (((DATASIZE) == SPI_DATASIZE_16BIT) || \                                            ((DATASIZE) == SPI_DATASIZE_8BIT))However:1. RM0477 [rev 10], section 55.3, Table 578 states that for SPI4 and SPI5 the data and CRC size is "configurable from 4 to 16 bits".2. The HAL itself is inconsistent. A few lines below the assert, the runtime check in HAL_SPI_Init() only rejects sizes above 16 bits for limited instances:if ((IS_SPI_LIM

I am using an STM32H755, and attempting to send 35 bytes of data over SPI.The data is copied into the TXDR, one byte at a time, but then only the first two bytes are send. The TSIZE is set to 35 and the CTSIZE counts down from 35 to 33, and then the TXDR bit goes high and no further data is sent. Could anyone suggest any reason why this may be happenning? Thanks

I got an issue with a STM32L432 project, were the MCU doesn't seem to behave according to the reference manual.This is the first time I deal with an L4xx variant, so I lack the experience with the clock tree of this devices.The sample code is a minimal Segger Embedded Studio application, with some printf() calls and an endless loop.The code works so far, I can flash and debug it.What doesn't work are my modifications to the clock configuration.Hardware is the L432 Nucleo-32 I got recently, just to mention it.The clock tree setup is basically the standard code, leaving MSI enabled in the default configuration (MSI, MSIRANGE=6, 4MHz), via functions SystemInit() and SystemCoreClockUpdate() in system_stm32l4xx.c.As modification, I tried to set a higher clock frequency, as MSI can be set in a range from 100kHz to 48MHz.However, I am not able to set a frequency higher than 8MHz (RCC->CR [MSIRANGE] = 7), writes to higher values are simply ignored.The code basically works (MSION = 1, MSIRGS

Hello ST team, I am trying to run an ONNX model on a NUCLEO-U545RE-Q board using STM32Cube AI Studio I first tried with a model of about 281.75 KiB weights, and the generated project failed at build/link stage with an undefined UART symbol. To check whether the issue was related to memory size, I also tried a smaller model: - Model: model_seqlen20.onnx- Input: f32(1x20x25)- Output: f32(1x1)- Parameters: 32,129- Weights: 128,516 B / 125.50 KiB- Activations: 2,256 B / 2.20 KiB- Total AI flash reported: 130,190 B- Target: stm32u5- Board: NUCLEO-U545RE-Q- Firmware package: STM32Cube_FW_U5_V1.9.0- ST Edge AI Core: v4.0.1-20581- Toolchain: STM32CubeIDE The model generation step completes successfully. The reported memory footprint is small enough for the board. However, during the Run flow, STM32Cube AI Studio the build fails with: undefined reference to `UartHandle` The errors are: Middlewares/ST/AI/Misc/Src/aiTestUtility.c:- _put_c_driver: undefined reference to `UartHandle`- ioRawWriteBuf

I am using the STM32CubeProgrammer v2.2.3 with MX66UW1G45G_STM32N6570-DK external loader for the STM32N6570-DK.After reloading the STM32N6570-DK demo that came with the kit, I get the following error message (see below). Most of the demo runs normally except the AI demo won’t run at all now (nothing on the display). LEDs LD3 and LD4 turn red only when the AI demo is selected from the menu. NOTE: I can download a new GUI from TouchGFX with no issues at all. Here is the log...09:05:48 : Disconnected from device.09:05:59 : UR connection mode is defined with the SWrst reset mode09:06:00 : Warning: Device changed, refreshing...09:06:00 : UR connection mode is defined with the SWrst reset mode09:06:00 : ST-LINK SN  : 002700193235510E3836373009:06:00 : ST-LINK FW  : V3J15M609:06:00 : Board       : STM32N6570-DK09:06:00 : Voltage     : 3.29V09:06:00 : SWD freq    : 8000 KHz09:06:00 : Connect mode: Hot Plug09:06:00 : Reset mode  : Software reset09:06:00 : Device ID   : 0x48609:06:00 : Revision