SPI Only sending 2 bytes and then TXTF flag goes high

[TomC1]

I am using an STM32H755, and attempting to send 35 bytes of data over SPI.

The data is copied into the TXDR, one byte at a time, but then only the first two bytes are send. The TSIZE is set to 35 and the CTSIZE counts down from 35 to 33, and then the TXDR bit goes high and no further data is sent. 

Could anyone suggest any reason why this may be happenning?

 

Thanks

[TDK]

If there are no error flags set then you’re probably missing something in your assumptions. Show a minimal (non-)working example.

[TDK]

Note that the TXFIFO can’t hold 35 bytes. If you’re blindly sending them all there immediately, that’s the problem.

[rich.g.williams]

If you set TSIZE to 1 it will send continuously. Here is my working test code:-

 

@STM32H5E5ZJ

@this test code sends a 32 bit word at regular intervals
@SCLK is 4MHz, peripheral clock is 248MHz 

@enable TIM2 to count down
ldr r0,=TIM2_BASE; ldr r1,=0x11; str r1,[r0,#TIM2_CR1]
ldr r0,=SPI1_BASE

@32-bit data /16 prescaler SPI1_CFG1
ldr r1,=(0x03<<28)|(0x1f<<0); str r1,[r0,#SPI1_CFG1]

@master Hardware NSS SPI1_CFG2
ldr r1,=(1<<31)|(1<<29)|(1<<22); str r1,[r0,#SPI1_CFG2]

@TSIZE set to 1 SPI1_CR2
ldr r1,=0x00; str r1,[r0,#SPI1_CR2]

@enable SPI peripheral SPE bit 0 in SPI1_CR1
ldr r1,[r0,#SPI1_CR1]; orr r1,r1,#0x1; str r1,[r0,#SPI1_CR1]

@start transfer CSTART bit 9 in SPI1_CR1
ldr r1,[r0,#SPI1_CR1]; orr r1,r1,#(1<<9); str r1,[r0,#SPI1_CR1]

@keep reloading TXDR and then delaying
ldr r1,=TIM2_BASE; ldr r3,[r1,#TIM2_CNT]

tx_loop: str r3,[r0,#SPI1_TXDR]; subs r3,r3,#0x1000
time1: ldr r4,[r1,#TIM2_CNT]; subs r4,r4,r3; bpl time1; b tx_loop

 

[Saket_Om]

Hello ​@TomC1 

Could you please share the content of the status register when it stops transmitting. 
 

[TomC1]

I am replying to my own question as I eventually figured out what was going wrong.

As a part of my application I need to quickly switch SPI modes. My process to do that is to disable the SPI, set the register bits for CPha and CPol, and then reenable the SPI.

Then later, I use the HAL_SPI_Transmit() function. The internals of this HAL function sets the correct TSIZE and then loads data into the TXDR. 

However! You cannot set the TSIZE while the SPI is enabled! If you query the contents of the SPI_CR2 register, it looks as though TSIZE is set correctly, but I think this register is only read when you enable SPI, because it seems to still use the previous value, which, in my case, was 2.

The fix was simply NOT to enable the SPI when switching modes. Now the HAL_SPI_Transmit() function is able to set everything correctly, and then enable the SPI itself.