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SZano · 2024-09-06

Is it ok to keep unused peripherals in perpetual reset, by leaving their RCC_APBRSTR_*RST (or similar) bit set?Maybe differences in power consumption?This is not for a specific STM32 family.I'm just looking for advice by people with more experience, ...

SZano · 2024-09-05

As explained in the reference manual RM0503 rev2, §14.10, the MCU has an internal bandgap voltage reference, which can be measured by the ADC peripheral. This reading can be compared to the one performed by ST in the factory (and stored in flash), so...

SZano · 2024-08-30

I'm using STM32CubeMX 6.12.0, with the firmware package U0_V1.1.0.When generating code for a STM32U073, the file system_stm32u0xx.c is generated, which contains the implementation of the SystemCoreClockUpdate() function.This file seems to be a mere c...

SZano · 2024-08-29

* In the reference manual RM0503 rev2, in §5.4.4 (description of RCC_PLLCFGR), the description of PLLR[2:0] indicates:Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.* In the reference manual RM0503 rev2, in §5.2...

SZano · 2024-08-29

The reference manual RM0503 rev2 has inconsistent information about the flash wait states.Table 9 in §3.3.4 shows three options: 0WS, 1WS, 2WS (and, by the way, it says that all three of them correspond to "1 CPU cycle", which seems wrong).Instead, §...

SZano · 2024-09-06

At startup it's better to reset everything (e.g. in case a faulty bootloader leaves some peripherals in an unknown state); then, why not leave them in reset until you actually need them? When you do, you clock them, and then take them out of reset. I...

SZano · 2024-09-05

My package is UFQFPN48.The date seems to be 345, so it must be this errata.Thanks

SZano · 2024-09-04

By looking at various .svd files, it seems that LDORDY only exists in (some) STM32H7, STM32U5, STM32WL, so I guess that in STM32U0 it doesn't exist, and it's just a copy-and-paste mistake.It would be nice to have some official confirmation, as well a...

SZano · 2024-09-03

@STTwo-32 Is there any update on this issue?What is LDORDY? Is it a bit that exists in other families, but not this one?Or is it a typo for some other flag (maybe ADC_ISR_CCRDY, though it seems to apply to regular conversions, not the calibration)?

SZano · 2024-07-09

Thanks for the information.However, I still have doubts.From my tests, everything works (even when single-stepping) as long as I don't freeze TIM9. So, it seems the issue is not related to halting the CPU. Also, I would expect the CPU to be halted, b...

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Keeping peripherals in perpetual reset

STM32U073CC - VREFINT calibration data (missing value / wrong documentation)

STM32U073 bug in SystemCoreClockUpdate()

STM32U073 - wrong documentation for clock frequency

STM32U073 flash wait states - wrong documentation

Re: Keeping peripherals in perpetual reset

Re: STM32U073CC - VREFINT calibration data (missing value / wrong documentation)

Re: LDORDY bit not found

Re: LDORDY bit not found

Re: TIM trigger is skipped while single-stepping with frozen TIM