STM32U073 - wrong documentation for clock frequency

[SZano]

* In the reference manual RM0503 rev2, in §5.4.4 (description of RCC_PLLCFGR), the description of PLLR[2:0] indicates:
Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.

* In the reference manual RM0503 rev2, in §5.2.9, table 32, the maximum PLLRCLK for "Range 1" is indicated as 56MHz.

* In the datasheet DS14548 rev2, in Table 56, fPLL_R_OUT is indicated as min 12MHz, max 64MHz (for range 1), and as min 12MHz, max 16MHz (for range 2)

* STM32CubeMX imposes a limit of 56MHz for the PLLR output (it's unclear which voltage range is used -- is it calculated or configured?)

Similar issues exist for the limits regarding PLLP, PLLQ, PLLN (especially in the RM).

The RM, datasheet, and/or CubeMX should be corrected so that they are all consistent. Also, the lower limits (and the fact that the limits depend on the voltage range) should be mentioned in the RM too.

[Sarra.S]

Hello @SZano, 

I'm checking these values internally ( Internal ticket 189772 Submitted) 

I will update you ASAP!

[Sarra.S · Accepted solution]

Hello again @SZano, 

You can refer to table 32 in RM as the correct one! The maximum PLLRCLK for "Range 1" is 56MHz.

DS will be updated.