About KDJEM.1

KDJEM.1 · 2024-09-25

Introduction The purpose of this article is to provide some external memories tips and tricks, frequently asked questions, and a list for useful link resources. 1. Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI 1.1. How to check whether a device is sup...

KDJEM.1 · 2024-08-05

There are two possible solutions for connecting two quad-SPI memories using only one OCTOSPI interface. Solution 1: Use a dedicated bit in the OCTOSPI_CR register for external memory selection: MSEL bit for STM32H5, STM32U5, and STM32L5 series or FS...

KDJEM.1 · 2024-07-30

Maximum FIFO size with the OCTOSPI interface The FIFO is sized into the targeted product, typically either 32 or 64 bytes depending on the product. Refer to the reference manual to check the maximum size in the "FIFO and data management" section. Co...

KDJEM.1 · 2024-06-10

Introduction This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available. The purpose of this article is to deliv...

KDJEM.1 · 2024-06-06

Introduction This article includes preliminary updates of STM32 MCU errata sheets reported since 1st January 2024. It highlights the current description requiring update and the expected one if available. The purpose of this article is to deliver an...

KDJEM.1 · 2024-11-19

Hello @MHana.1 , To increase the probably of obtaining a answer, could you please share your project and errors screenshot? May this post can help you. Thank you. Kaouthar

KDJEM.1 · 2024-11-19

Hello @Harry_Wan and welcome to the community, To increase the probably of obtaining a answer, could you please share your project and more details about "build output"? Thank you. Kaouthar

KDJEM.1 · 2024-11-19

Hello @Jinchen , Could you please give more detail about this hardfault? Is the optimization level set to 0? May this FAQ "How to debug a HardFault on an Arm Cortex®-M STM32" can help you. This article can help you to learn about fault registers, ...

KDJEM.1 · 2024-11-19

Hello @tobbymathew and welcome to the Community, For STM32F429, the total embedded SRAM size is 256 Kbytes and 4 Kbytes of backup SRAM. So, you need to check if the frame can be located in the internal SRAM or the size of frame buffer exceeds th...

KDJEM.1 · 2024-11-18

Hello @colin0325 and welcome to the Community, Could you please check the data enable polarity and GPIO speed mode? The LTDC control signals (HSYNC, VSYNC, DE, and LCD_CLK) polarities must be configured respecting thedisplay specifications.Note: Only...

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Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI

How to connect two quad-SPI memories using only one OCTOSPI

FAQ: How to configure FIFO with the OCTOSPI interface

STM32 MCU reference manuals: Expected preliminary updates

STM32 MCU errata sheets: Expected preliminary updates

Re: STM32H7B3I with appwizard GUI using Keil, can not build project?

Re: STM32H74 problem

Re: HardDefault when using DSP arm filer

Re: Parallel TFT Display not working

Re: Black screen with STM32H7A3 LTDC