How to connect two quad-SPI memories using only one OCTOSPI

[KDJEM.1]

There are two possible solutions for connecting two quad-SPI memories using only one OCTOSPI interface.

Solution 1:

Use a dedicated bit in the OCTOSPI_CR register for external memory selection: MSEL bit for STM32H5, STM32U5, and STM32L5 series or FSEL bit for STM32H7 and STM32L4+ series: The idea is to select the external memory to be addressed in single-, dual-, quad-SPI mode in a single-memory configuration.
MSEL or FSEL bit configuration:
0: External memory 1 selected (data exchanged over IO[3:0])
1: External memory 2 selected (data exchanged over IO[7:4])
This MSEL/FSEL bit is ignored when DMM = 1 or when octal-SPI mode is selected.

Figure 1: Connecting 2xQuadSPI memories using only one OCTOSPI interface.

Solution 2:

Use a different chip select GPIO pins for each memory. The two memories must be connected to the same OCTOSPI instance. The chip select of each memory must be connected to an OCTOSPI chip select GPIO pin as shown in the below figure. 

The software should configure the chip to select the GPIO pin for the memory to be accessed by driving the GPIO configuration. For example, when transmitting data to quad-SPI memory1, it is recommended to set the quad-SPI memory2 chip select pin (Pin2) to high voltage by using a pull-up resistor. In this case, the GPIO Pin2 is configured as GPIO output "Pull-up" and the Pin1 is configured as an alternate function.

Figure 2: Connecting 2xQuadSPI memories using only one OCTOSPI interface.

 Notes

• These two proposed solutions can be applied when using identical or different types of quad-SPI memories.
• In case of two different memories, before switching from quad-SPI memory to another, it is recommended to reconfigure the OCTOSPI interface accordingly the desired memory specification.
• Please wait for data transmission to be completed before switching from quad-SPI memory to another.

[lenonrteng]

Is it possible to use memory-mapped mode in both solution on STM32U5?

[KDJEM.1]

Hello @lenonrteng and welcome to the Community ;

Yes, you can use “memory-mapped” mode for both solutions on STM32U5.

Thank you for your contribution in STCommunity.

Kaouthar

[MMARI.1]

hi, @KDJEM.1 @lenonrteng @Raouf @Kaouther BELHADJ ,

Can you suggest   bsp examples code (how to manage dual quad into single octal ) for solution no. 1.

[ST_Doogie]

Hello,

Is it also possible to have each QSPI device operate in a different mode? I'd like to operate a QSPI PSRAM in memory mapped mode with reads and writes possible and a QSPI Flash chip as an onboard mass storage device in "block" mode. I'm assuming I'd need to utilize two OctoSPI instances to be able to DMA to both simultaneously.

I'm also aware of Hyperbus devices which have both PSRAM and Flash in one package via stacked die and separate chip select pins. Since they share data pins, they cannot be accessed simultaneously, but I would assume these devices would also like to operate with the PSRAM as memory mapped and the flash as a block accessed mass storage-like device.

I'm sure it's possible to achieve the above sans simultaneous DMA by re-configuring the OctoSPO/XSPI peripheral for every mode shift, but it would be nice if the connection scheme above with the split 8-bit data bus could be configured for different modes on each nybble.

Other than that, thanks for clarifying how the data bus is either split or shared and the chip select is logically shared as I am used to the G4's dual bank style QSPI which has separate chip selects, but is incapable of writes in memory mapped mode.

Thanks and Best Regards.

[MMARI.1]

hi,

thanks for clarifying i understood that dual QSPI can used as separate qspi 1& qspi  2 not integrated octal . 

seems STM32H7R7/7S7 is better for to use octal flash , Since XiP mode available  .