Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI

KDJEM.1 · ‎2024-09-25

Introduction

The purpose of this article is to provide some external memories tips and tricks, frequently asked questions, and a list for useful link resources.

1. Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI

1.1. How to check whether a device is supported

In order to start, the user must verify if these interfaces are supported by the device. The command format and order shared in the device datasheet must be aligned with the command format and order mentioned in the STM32 reference.

1.2. The maximum frequency

Refer to the memory datasheet and the STM32 datasheet to check the maximum allowed frequency. The adequate frequency must be supported by the memory and the interfaces.

1.3. Limitations and workarounds listed

Check the STM32 MCU errata sheet regarding your device for any known limitations and workarounds.

1.4. Should the cache be disabled or enabled?

We recommend disabling the cache to avoid masking issues.

1.5. Can I use the interfaces as classic-SPI?

The controllers interfaces work only as masters and support the Single-SPI (legacy-SPI). The interfaces do not support full duplex. Therefore, it cannot send and receive data simultaneously.

1.6. How to calculate the chip select high time

Chip select high time defines the chip-select minimum high time in number of clock interface cycles, tCPH / clock interface cycle. Round up the found value to the next integer value, configured depending on the memory datasheet.

Note that the clock interface cycle provided to the external memory equal to (clock cycle / (PRESCALER+1)), with PRESCALER[7:0] is configured in QUADSPI_CR/OCTOSPI_DCR2/HSPI_DCR2/ XSPI_DCR2 registers for the respective interfaces.

1.7. When is sample shifting and delay hold quarter cycle used?

Sample shifting (SSHT) should be enabled in STR mode and disabled in DTR mode. Delay hold quarter cycle (DHQC) should be enabled in DTR mode and disabled in STR mode.

2. FAQs specifically for QUADSPI

2.1. Does the QUADSPI support write operations in memory-mapped mode?

For the QUADSPI, in memory-mapped mode, the external flash memory is seen as an internal memory but with some latency during accesses. Only read operations are allowed to the external flash memory in memory-mapped mode. The indirect mode supports read and write operations. For the OCTOSPI interface, the write operation is supported in memory-mapped mode.

3. FAQs specifically for OCTOSPI

3.1. Which memory type should be used for the Quad-SPI mode configuration?

The memory type has no impact in Quad-SPI mode.

3.2. Which memory type should be used for the Octo-SPI mode configuration?

You simply need to look at the data ordering in the memory datasheet and then select the one that matches it in the STM32 OCTOSPI configuration. The micron (and compatible memories) use D0/D1 ordering while Macronix (and compatible memories) use D1/D0 data ordering.

3.3. How to calculate the chip select boundary

Chip select boundary (CSBOUND) is configured depending on the memory datasheet and required for RAM memory. The chip select must go high when crossing the page boundary (2^CSBOUNDbytes defines the page size).

3.4. When is Refresh Rate used and how is it calculated?

Refresh rate (REFRESH) is required for PSRAMs memories. The chip select must go high each (REFRESH x OCTOSPI clock cycles), configured depending on the memory datasheet.

3.5. How to configure the write zero latency

Write zero latency enabled (WZL) defines the latency on write accesses. So, the configuration for the "WriteZeroLatency" parameter in the "HyperBus" mode depends on the specific requirements of your application and the behavior of the memory device you are interfacing with. Here are the two options:

Enable: This setting enables latency on write operations. It is typically used when the memory device requires additional time to process write commands. This can help ensure data integrity and proper timing.
Disable: This setting disables latency on write operations. It is used when the memory device can handle write commands without needing additional time for processing. This can improve write performance by reducing delays.