Defining HSLV
HSLV is a characteristic of certain I/O ports that allows them to operate at higher speeds while using lower voltage levels. This feature is particularly useful for applications that require fast data transfer rates without the higher power consumption typically associated with standard voltage levels.
Caution for HSLV on the STM32H7RS
The HSLV is only activated when VDD ≤ 2.7 V. This feature should not be used at a voltage higher than 2.7 V, it can lead to unexpected behavior.
The I/O HSLV configuration bit must not be set if the I/O supply (VDD) is above 2.7 V. Setting it while the voltage is higher than 2.7 V can damage the device.
For that, the I/O HSLV bits (VDDIO_HSLV, XSPI1_HSLV and XSPI2_HSLV) by default are 0 on STM32H7RS to avoid damaging the device if the voltage is higher than 2.7 V.
Except for STM32H7S78-DK, these bits are set by default to 1 as a graphic demo from external flash is implemented on it and requires HSLV bits equal to 1.
How to configure HSLV bits on the STM32H7RS
1. Open STM32CubeProgrammer.
2. Click on [Connect].
3. Click on the [OB] option bytes and then [User configuration1].
4. Choose the HSLV bits levels and then click on [Apply].
Recommendations for HSLV on the STM32H7RS
Enabling HSLV is recommended in cases when the XSPIM domain is powered by 1.8 V and is operating the serial memory interface at its maximum speed of 200 MHz.
If you run an STM32Cube_FW_H7RS example, it is recommended to check the readme file for the HSLV bits level.
